Takashi Manabe

According to our database, Takashi Manabe authored at least 3 papers between 1994 and 2000.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2000

Dynamic Stability Analysis of Flow-Conveying Pipe with Two Lumped Masses by Domain Decomposition BEM.

Takashi Manabe, Nobuyoshi Tosaka, Toshio Honma

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

1995

Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications.

Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina

IEEE J. Solid State Circuits, June, 1995

1994

A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM.

Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina

IEEE J. Solid State Circuits, November, 1994