Kazuyuki Nakamura

According to our database, Kazuyuki Nakamura authored at least 31 papers between 1994 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Effective mechanical potential of cell-cell interaction explains three-dimensional morphologies during early embryogenesis.

Hiroshi Koyama, Hisashi Okumura, Atsushi M. Ito, Kazuyuki Nakamura, Tetsuhisa Otani, Kagayaki Kato, Toshihiko Fujimori

PLoS Comput. Biol., 2023

2022

Real-time Linear Operator Construction and State Estimation with the Kalman Filter.

Tsuyoshi Ishizone, Kazuyuki Nakamura

J. Inf. Process., 2022

Occupancy Detection for General Households by Bidirectional LSTM with Attention.

Hisashi Oshima, Tsuyoshi Ishizone, Kazuyuki Nakamura, Tomoyuki Higuchi

Proceedings of the IECON 2022, 2022

An Online System of Detecting Anomalies and Estimating Cycle Times for Production Lines.

Tsuyoshi Ishizone, Tomoyuki Higuchi, Kosuke Okusa, Kazuyuki Nakamura

Proceedings of the IECON 2022, 2022

2021

The Application of Zig-Zag Sampler in Sequential Markov Chain Monte Carlo.

Yu Han, Kazuyuki Nakamura

CoRR, 2021

2020

Ensemble Kalman Variational Objectives: Nonlinear Latent Trajectory Inference with A Hybrid of Variational Inference and Ensemble Kalman Filter.

Tsuyoshi Ishizone, Tomoyuki Higuchi, Kazuyuki Nakamura

CoRR, 2020

Identifying Snowfall Clouds at Syowa Station, Antarctica via a Convolutional Neural Network.

Kazue Suzuki, Masaki Shimomura, Kazuyuki Nakamura, Naohiko Hirasawa, Hironori Yabuki, Takashi Yamanouchi, Terumasa Tokunaga

Proceedings of the Advances in Artificial Intelligence, 2020

2018

Multiresolutional Hierarchical Bayesian NMF for Detailed Audio Analysis of Music Performances.

Takeshi Hori, Kazuyuki Nakamura, Shigeki Sagayama

Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2018

2017

Music chord recognition from audio data using bidirectional encoder-decoder LSTMs.

Takeshi Hori, Kazuyuki Nakamura, Shigeki Sagayama

Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017

2012

Extraction of groove feelings from drum data using non-negative matrix factorization.

Yoshito Ohya, Kazuyuki Nakamura, Terumasa Tokunaga

Proceedings of the 6th International Conference on Soft Computing and Intelligent Systems (SCIS), 2012

Instability caused by the cubic potential in the foreign exchange market observed at the intervention by the Bank of Japan.

Yoshihiro Yura, Misako Takayasu, Hideki Takayasu, Kazuyuki Nakamura

Proceedings of the 15th International Conference on Information Fusion, 2012

2011

An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O.

Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura

IEICE Trans. Electron., 2011

Sequential data assimilation in geotechnical engineering and its application to seepage analysis.

Kazuyuki Nakamura, Shinya Yamamoto, Makoto Honda

Proceedings of the 14th International Conference on Information Fusion, 2011

2010

A Knowledge Sharing System for Software Developers.

Takayuki Shibata, Kazuyuki Nakamura, Takanobu Sato, Rentaro Yoshioka

Proceedings of the ICSOFT 2010, 2010

An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function.

Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Parameter Estimation of In Silico Biological Pathways with Particle Filtering Towards a Petascale Computing.

Kazuyuki Nakamura, Ryo Yoshida, Masao Nagasaki, Satoru Miyano, Tomoyuki Higuchi

Proceedings of the Biocomputing 2009: Proceedings of the Pacific Symposium, 2009

2007

A Recursive Recomputation Approach for Smoothing in Nonlinear State-Space Modeling: An Attempt for Reducing Space Complexity.

Kazuyuki Nakamura, Takashi Tsuchiya

IEEE Trans. Signal Process., 2007

2006

Sequential Data Assimilation: Information Fusion of a Numerical Simulation and Large Scale Observation Data.

Kazuyuki Nakamura, Tomoyuki Higuchi, Naoki Hirose

J. Univers. Comput. Sci., 2006

2005

An Improvement of ITU-T G.711 Packet Loss Concealment.

Keiichi Funaki, Kazuyuki Nakamura

Proceedings of the Internet and Multimedia Systems and Applications, 2005

2001

A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture.

Kouichi Yamaguchi, Muneo Fukaishi, Takehiko Sakamoto, Naoto Akiyama, Kazuyuki Nakamura

IEEE J. Solid State Circuits, 2001

Optimizing bias-circuit design of cascode operational amplifier for wide dynamic range operations.

Takeshi Fukumoto, Hiroyuki Okada, Kazuyuki Nakamura

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Optical interconnection as an IP macro of a CMOS library.

Takashi Yoshikawa, Ichiro Hatakeyama, Kazunori Miyoshi, Kazuhiko Kurata, Juni-Ichi Sasaki, Nobuharu Kami, Takara Sugimoto, Muneo Fukaishi, Kazuyuki Nakamura, Kei Tanaka, Hiroaki Nishi, Tomohiro Kudoh

Proceedings of the Ninth Symposium on High Performance Interconnects, 2001

A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO.

Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000

A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays.

Muneo Fukaishi, Kazuyuki Nakamura, Hideki Heiuchi, Yoshinori Hirota, Yoetsu Nakazawa, Hidenori Ikeno, Hiroshi Hayama, Michio Yotsuyanagi

IEEE J. Solid State Circuits, 2000

1998

A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture.

Muneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, Yutaka Tsutsui, Syuji Kishi, Michio Yotsuyanagi

IEEE J. Solid State Circuits, 1998

1997

A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O.

Kazuyuki Nakamura, Koichi Takeda, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto

IEEE J. Solid State Circuits, 1997

1996

A 3.84 gips integrated memory array processor.

Yoshihiro Fujita, Nobuyuki Yamashita, Tohru Kimura, Kazuyuki Nakamura, Shin'ichiro Okazaki

Syst. Comput. Jpn., 1996

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM.

Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki

IEEE J. Solid State Circuits, 1996

1995

Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications.

Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina

IEEE J. Solid State Circuits, June, 1995

1994

A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM.

Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina

IEEE J. Solid State Circuits, November, 1994

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator.

Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki

IEEE J. Solid State Circuits, November, 1994