Tali Moreshet

According to our database, Tali Moreshet authored at least 26 papers between 2003 and 2022.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2022

HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures.

Jiwon Choe, Andrew Crotty, Tali Moreshet, Maurice Herlihy, R. Iris Bahar

Proceedings of the SPAA '22: 34th ACM Symposium on Parallelism in Algorithms and Architectures, Philadelphia, PA, USA, July 11, 2022

Towards Hardware Accelerated Garbage Collection with Near-Memory Processing.

Samuel Thomas, Jiwon Choe, Ofir Gordon, Erez Petrank, Tali Moreshet, Maurice Herlihy, R. Iris Bahar

Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

2020

Voltage Noise Mitigation With Barrier Approximation.

Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu

IEEE Comput. Archit. Lett., 2020

2019

Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation.

Jiwon Choe, Amy Huang, Tali Moreshet, Maurice Herlihy, R. Iris Bahar

Proceedings of the 31st ACM on Symposium on Parallelism in Algorithms and Architectures, 2019

Attacking memory-hard scrypt with near-data-processing.

Jiwon Choe, Tali Moreshet, R. Iris Bahar, Maurice Herlihy

Proceedings of the International Symposium on Memory Systems, 2019

Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis.

Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu

Proceedings of the IEEE International Symposium on Workload Characterization, 2019

IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM.

Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures.

Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar

Int. J. Parallel Program., 2018

2017

Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency.

Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Maurice Herlihy, R. Iris Bahar

ACM Trans. Embed. Comput. Syst., 2017

Evaluating critical bits in arithmetic operations due to timing violations.

Sungseob Whang, Tymani Rachford, Dimitra Papagiannopoulou, Tali Moreshet, R. Iris Bahar

Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2016

Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems.

Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar

Proceedings of the 2016 International Conference on Compilers, 2016

2015

Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems.

Dimitra Papagiannopoulou, Giuseppe Capodanno, Tali Moreshet, Maurice Herlihy, R. Iris Bahar

ACM Trans. Embed. Comput. Syst., 2015

Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution.

Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Speculative synchronization for coherence-free embedded NUMA architectures.

Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

2013

Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs.

Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini

Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

2011

Power-Performance Comparison of Single-Task Driven Many-Cores.

Fuat Keceli, Tali Moreshet, Uzi Vishkin

Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011

SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs.

Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R. Iris Bahar, Tali Moreshet, Luca Benini, Maurice Herlihy

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010

Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems.

Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy

J. Parallel Distributed Comput., 2010

Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems.

Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy

Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Thermal Management of a Many-Core Processor under Fine-Grained Parallelism.

Fuat Keceli, Tali Moreshet, Uzi Vishkin

Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2010

2008

Energy efficient synchronization techniques for embedded architectures.

Cesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

A hardware/software framework for supporting transactional memory in a MPSoC environment.

Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy

SIGARCH Comput. Archit. News, 2007

2006

Energy implications of multiprocessor synchronization.

Tali Moreshet, R. Iris Bahar, Maurice Herlihy

Proceedings of the SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30, 2006

2005

Energy reduction in multiprocessor systems using transactional memory.

Tali Moreshet, R. Iris Bahar, Maurice Herlihy

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

2004

Effects of speculation on performance and issue queue design.

Tali Moreshet, R. Iris Bahar

IEEE Trans. Very Large Scale Integr. Syst., 2004

2003

Power-aware issue queue design for speculative instructions.

Tali Moreshet, R. Iris Bahar

Proceedings of the 40th Design Automation Conference, 2003