Tali Moreshet

According to our database1, Tali Moreshet authored at least 22 papers between 2003 and 2019.

Collaborative distances:



In proceedings 
PhD thesis 


On csauthors.net:


Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation.
Proceedings of the 31st ACM on Symposium on Parallelism in Algorithms and Architectures, 2019

Attacking memory-hard scrypt with near-data-processing.
Proceedings of the International Symposium on Memory Systems, 2019

IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures.
International Journal of Parallel Programming, 2018

Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency.
ACM Trans. Embedded Comput. Syst., 2017

Evaluating critical bits in arithmetic operations due to timing violations.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems.
Proceedings of the 2016 International Conference on Compilers, 2016

Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems.
ACM Trans. Embedded Comput. Syst., 2015

Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Speculative synchronization for coherence-free embedded NUMA architectures.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

Power-Performance Comparison of Single-Task Driven Many-Cores.
Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011

SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems.
J. Parallel Distrib. Comput., 2010

Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Thermal Management of a Many-Core Processor under Fine-Grained Parallelism.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2010

Energy efficient synchronization techniques for embedded architectures.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A hardware/software framework for supporting transactional memory in a MPSoC environment.
SIGARCH Computer Architecture News, 2007

Energy implications of multiprocessor synchronization.
Proceedings of the SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30, 2006

Energy reduction in multiprocessor systems using transactional memory.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Effects of speculation on performance and issue queue design.
IEEE Trans. VLSI Syst., 2004

Power-aware issue queue design for speculative instructions.
Proceedings of the 40th Design Automation Conference, 2003