Ulya R. Karpuzcu

Orcid: 0000-0001-9238-4256

According to our database1, Ulya R. Karpuzcu authored at least 72 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization.
Dataset, January, 2024

On Gate Flip Errors in Computing-In-Memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
3SAT on an All-to-All-Connected CMOS Ising Solver Chip.
CoRR, 2023

On Endurance of Processing in (Nonvolatile) Memory.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

PimCity: A Compute in Memory Substrate featuring both Row and Column Parallel Computing.
Proceedings of the IEEE International Conference on Rebooting Computing, 2023

2022
Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions.
ACM Trans. Embed. Comput. Syst., September, 2022

CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM.
IEEE Trans. Emerg. Top. Comput., 2022

GeNVoM: Read Mapping Near Non-Volatile Memory.
IEEE ACM Trans. Comput. Biol. Bioinform., 2022

Benchmarking Quantum Computers and the Impact of Quantum Noise.
ACM Comput. Surv., 2022

Error Detection and Correction for Processing in Memory (PiM).
CoRR, 2022

On Variable Strength Quantum ECC.
IEEE Comput. Archit. Lett., 2022

2021
Trading Computation for Communication: A Taxonomy of Data Recomputation Techniques.
IEEE Trans. Emerg. Top. Comput., 2021

Spiking Neural Networks in Spintronic Computational RAM.
ACM Trans. Archit. Code Optim., 2021

Special Issue on Quantum Computing.
IEEE Micro, 2021

Towards Homomorphic Inference Beyond the Edge.
CoRR, 2021

Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator.
CoRR, 2021

On Value Recomputation to Accelerate Invisible Speculation.
CoRR, 2021

A Day In the Life of a Quantum Error.
IEEE Comput. Archit. Lett., 2021

Cryogenic PIM: Challenges & Opportunities.
IEEE Comput. Archit. Lett., 2021

Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation.
Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

Seeds of SEED: H-CRAM: In-memory Homomorphic Search Accelerator using Spintronic Computational RAM.
Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

CAMeleon: Reconfigurable B(T)CAM in Computational RAM.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
PIMBALL: Binary Neural Networks in Spintronic Memory.
ACM Trans. Archit. Code Optim., 2020

An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM).
CoRR, 2020

Dual-precision fixed-point arithmetic for low-power ray-triangle intersections.
Comput. Graph., 2020

Voltage Noise Mitigation With Barrier Approximation.
IEEE Comput. Archit. Lett., 2020

MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

ACR: Amnesic Checkpointing and Recovery.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation.
IEEE Trans. Very Large Scale Integr. Syst., 2019

In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping.
IEEE Trans. Computers, 2019

A Machine Learning Accelerator In-Memory for Energy Harvesting.
CoRR, 2019

Special Session: Does Approximation Make Testing Harder (or Easier)?
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

POWERT Channels: A Novel Class of Covert CommunicationExploiting Power Management Vulnerabilities.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

True In-memory Computing with the CRAM: From Technology to Applications.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Approximate Ultra-Low Voltage Many-Core Processor Design.
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018
On Approximate Speculative Lock Elision.
IEEE Trans. Multi Scale Comput. Syst., 2018

Toward Dynamic Precision Scaling.
IEEE Micro, 2018

Approximate Communication: Techniques for Reducing Communication Bottlenecks in Large-Scale Parallel Systems.
ACM Comput. Surv., 2018

Computational RAM to Accelerate String Matching at Scale.
CoRR, 2018

Exploiting Processing in Non-Volatile Memory for Binary Neural Network Accelerators.
CoRR, 2018

AISC: Approximate Instruction Set Computer.
CoRR, 2018

A New Class of Covert Channels Exploiting Power Management Vulnerabilities.
IEEE Comput. Archit. Lett., 2018

On Memory System Design for Stochastic Computing.
IEEE Comput. Archit. Lett., 2018

Efficient In-Memory Processing Using Spintronics.
IEEE Comput. Archit. Lett., 2018

Mitigation of NBTI induced performance degradation in on-chip digital LDOs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing Among Distributed On-Chip Voltage Regulators.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Recomputation Enabled Efficient Checkpointing.
CoRR, 2017

Trading Computation for Communication: A Taxonomy.
CoRR, 2017

On Dynamic Precision Scaling.
CoRR, 2017

A Non-volatile Near-Memory Read Mapping Accelerator.
CoRR, 2017

ThermoGater: Thermally-Aware On-Chip Voltage Regulation.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

AMNESIAC: Amnesic Automatic Computer.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Accuracy Bugs: A New Class of Concurrency Bugs to Exploit Algorithmic Noise Tolerance.
ACM Trans. Archit. Code Optim., 2016

Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Decoupled Control and Data Processing for Approximate Near-Threshold Voltage Computing.
IEEE Micro, 2015

Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Accordion: Toward soft Near-Threshold Voltage Computing.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Coping with Parametric Variation at Near-Threshold Voltages.
IEEE Micro, 2013

EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
Novel many-core architectures for energy-efficiency
PhD thesis, 2012

VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks, 2012

2010
LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2009
The BubbleWrap many-core: popping cores for sequential acceleration.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Accurate microarchitecture-level fault modeling for studying hardware faults.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Blueshift: Designing processors for timing speculation from the ground up.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2005
Automatic verilog code generation through grammatical evolution.
Proceedings of the Genetic and Evolutionary Computation Conference, 2005


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