Thomas Carle

Orcid: 0000-0002-1411-1030

Affiliations:
  • Paul Sabatier University, Toulouse, France
  • Brown University, Providence, Rhode Island, USA (former)


According to our database1, Thomas Carle authored at least 21 papers between 2014 and 2023.

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Bibliography

2023
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Extending a predictable machine learning framework with efficient gemm-based convolution routines.
Real Time Syst., September, 2023

MINOTAuR: A Timing Predictable RISC-V Core Featuring Speculative Execution.
IEEE Trans. Computers, 2023

Warp-Level CFG Construction for GPU Kernel WCET Analysis.
Proceedings of the 21th International Workshop on Worst-Case Execution Time Analysis, 2023

Validation of Processor Timing Models Using Cycle-Accurate Timing Simulators.
Proceedings of the 21th International Workshop on Worst-Case Execution Time Analysis, 2023

Enabling timing predictability in the presence of store buffers.
Proceedings of the 31st International Conference on Real-Time Networks and Systems, 2023

2022
A Framework for Calculating WCET Based on Execution Decision Diagrams.
ACM Trans. Embed. Comput. Syst., 2022

ACETONE: Predictable Programming Framework for ML Applications in Safety-Critical Systems (Artifact).
Dagstuhl Artifacts Ser., 2022

ACETONE: Predictable Programming Framework for ML Applications in Safety-Critical Systems.
Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

Correctness and Efficiency Criteria for the Multi-Phase Task Model.
Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

2021
Speculative Execution and Timing Predictability in an Open Source RISC-V Core.
Proceedings of the 42nd IEEE Real-Time Systems Symposium, 2021

Static Extraction of Memory Access Profiles for Multi-core Interference Analysis of Real-Time Tasks.
Proceedings of the Architecture of Computing Systems - 34th International Conference, 2021

2020
Improving the Performance of WCET Analysis in the Presence of Variable Latencies.
Proceedings of the 21st ACM SIGPLAN/SIGBED International Conference on Languages, 2020

2018
Reducing Timing Interferences in Real-Time Applications Running on Multicore Architectures.
Proceedings of the 18th International Workshop on Worst-Case Execution Time Analysis, 2018

2016
Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems.
Proceedings of the 2016 International Conference on Compilers, 2016

2015
From Dataflow Specification to Multiprocessor Partitioned Time-triggered Real-time Implementation.
Leibniz Trans. Embed. Syst., 2015

On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2015

2014
Compilation efficace de spécifications de contrôle embarqué avec prise en compte de propriétés fonctionnelles et non-fonctionnelles complexes. (Efficient compilation of embedded control specifications with complex functional and non-functional properties).
PhD thesis, 2014

Predicate-aware, makespan-preserving software pipelining of scheduling tables.
ACM Trans. Archit. Code Optim., 2014

Reconciling performance and predictability on a many-core through off-line mapping.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Static Mapping of Real-Time Applications onto Massively Parallel Processor Arrays.
Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014


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