Luca Benini

According to our database1, Luca Benini authored at least 872 papers between 1994 and 2018.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2016, "For contributions to the design of low power multi-processor systems".

IEEE Fellow

IEEE Fellow 2007, "For contributions to design technologies for low power design of integrated circuits and systems".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

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Homepages:

On csauthors.net:

Bibliography

2018
Quantifying the Impact of Variability and Heterogeneity on the Energy Efficiency for a Next-Generation Ultra-Green Supercomputer.
IEEE Trans. Parallel Distrib. Syst., 2018

Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes.
IEEE Trans. Parallel Distrib. Syst., 2018

The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores.
IEEE Trans. Multi-Scale Computing Systems, 2018

Towards Edge-Aware Spatio-Temporal Filtering in Real-Time.
IEEE Trans. Image Processing, 2018

Design and Evaluation of a Low-Power Sensor Device for Induced Rockfall Experiments.
IEEE Trans. Instrumentation and Measurement, 2018

Runtime Support for Multiple Offload-Based Programming Models on Clustered Manycore Accelerators.
IEEE Trans. Emerging Topics Comput., 2018

Energy-Aware Bio-Signal Compressed Sensing Reconstruction on the WBSN-Gateway.
IEEE Trans. Emerging Topics Comput., 2018

Efficient, Long-Term Logging of Rich Data Sensors Using Transient Sensor Nodes.
ACM Trans. Embedded Comput. Syst., 2018

A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing.
IEEE Trans. on Circuits and Systems, 2018

Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Lightweight IO virtualization on MPU enabled microcontrollers.
SIGBED Review, 2018

Leveraging Energy Harvesting and Wake-Up Receivers for Long-Term Wireless Sensor Networks.
Sensors, 2018

Long-short range communication network leveraging LoRa™ and wake-up receiver.
Microprocessors and Microsystems - Embedded Hardware Design, 2018

A Multi-Sensor and Parallel Processing SoC for Miniaturized Medical Instrumentation.
J. Solid-State Circuits, 2018

A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation.
J. Solid-State Circuits, 2018

Optimizing memory bandwidth exploitation for OpenVX applications on embedded many-core accelerators.
J. Real-Time Image Processing, 2018

An Energy Efficient E-Skin Embedded System for Real-Time Tactile Data Decoding.
J. Low Power Electronics, 2018

A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems.
Information Fusion, 2018

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures.
International Journal of Parallel Programming, 2018

A 2.2-µW Cognitive Always-On Wake-Up Circuit for Event-Driven Duty-Cycling of IoT Sensor Nodes.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Extended Bit-Plane Compression for Convolutional Neural Network Accelerators.
CoRR, 2018

Robust online identification of thermal models for in-production HPC clusters with machine learning-based data selection.
CoRR, 2018

KRATOS: An Open Source Hardware-Software Platform for Rapid Research in LPWANs.
CoRR, 2018

On-Demand TDMA for Energy Efficient Data Collection with LoRa and Wake-up Receiver.
CoRR, 2018

Slotted ALOHA Overlay on LoRaWAN: a Distributed Synchronization Approach.
CoRR, 2018

One-shot Learning for iEEG Seizure Detection Using End-to-end Binary Operations: Local Binary Patterns with Hyperdimensional Computing.
CoRR, 2018

Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine.
CoRR, 2018

CBinfer: Exploiting Frame-to-Frame Locality for Faster Convolutional Network Inference on Video Streams.
CoRR, 2018

On the Feasibility of FPGA Acceleration of Molecular Dynamics Simulations.
CoRR, 2018

Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory.
CoRR, 2018

XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference.
CoRR, 2018

COUNTDOWN - three, two, one, low power! A Run-time Library for Energy Saving in MPI Communication Primitives.
CoRR, 2018

Pricing Schemes for Energy-Efficient HPC Systems: Design and Exploration.
CoRR, 2018

Dwarf in a Giant: Enabling Scalable, High-Resolution HPC Energy Monitoring for Real-Time Profiling and Analytics.
CoRR, 2018

Ultra Low Power Deep-Learning-powered Autonomous Nano Drones.
CoRR, 2018

Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes.
CoRR, 2018

Efficient Image Dataset Classification Difficulty Estimation for Predicting Deep-Learning Accuracy.
CoRR, 2018

XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks.
CoRR, 2018

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets.
CoRR, 2018

An EMG Gesture Recognition System with Flexible High-Density Sensors and Brain-Inspired High-Dimensional Classifier.
CoRR, 2018

BinaryEye: A 20 kfps Streaming Camera System on FPGA with Real-Time On-Device Image Recognition Using Binary Neural Networks.
Proceedings of the 13th IEEE International Symposium on Industrial Embedded Systems, 2018

Pible: battery-free mote for perpetual indoor BLE applications: demo abstract.
Proceedings of the 5th Conference on Systems for Built Environments, 2018

Pible: battery-free mote for perpetual indoor BLE applications.
Proceedings of the 5th Conference on Systems for Built Environments, 2018

On the Cost of Freedom From Interference in Heterogeneous SoCs.
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018

Combining PREM compilation and ILP scheduling for high-performance and predictable MPSoC execution.
Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores, 2018

Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Design Automation for Binarized Neural Networks: A Quantum Leap Opportunity?
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An EMG Gesture Recognition System with Flexible High-Density Sensors and Brain-Inspired High-Dimensional Classifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Smart Wearable Wristband for EMG based Gesture Recognition Powered by Solar Energy Harvester.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An 826 MOPS, 210uW/MHz Unum ALU in 65 nm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Modal Analysis of Structures with Low-cost Embedded Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Combining LoRa and RTK to achieve a high precision self-sustaining geo-localization system: poster abstract.
Proceedings of the 17th ACM/IEEE International Conference on Information Processing in Sensor Networks, 2018

A Scalable Framework for Online Power Modelling of High-Performance Computing Nodes in Production.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

Rat Cortical Layers Classification extracting Evoked Local Field Potential Images with Implanted Multi-Electrode Sensor.
Proceedings of the 20th IEEE International Conference on e-Health Networking, 2018

An accurate low-cost Crackmeter with LoRaWAN communication and energy harvesting capability.
Proceedings of the 23rd IEEE International Conference on Emerging Technologies and Factory Automation, 2018

ALOHA: an architectural-aware framework for deep learning at the edge.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

ANTAREX: A DSL-Based Approach to Adaptively Optimizing and Enforcing Extra-Functional Properties in High Performance Computing.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

A transprecision floating-point platform for ultra-low power computing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

High speed ASIC implementations of leakage-resilient cryptography.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not?
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

HePREM: Enabling predictable GPU execution on heterogeneous SoC.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

PULP-HD: accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform.
Proceedings of the 55th Annual Design Automation Conference, 2018

XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

Quantized NNs as the definitive solution for inference on low-power ARM MCUs?: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

Chipmunk: A systolically scalable 0.9 mm2, 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018


Always-ON visual node with a hardware-software event-based binarized neural network inference engine.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

QUENN: QUantization engine for low-power neural networks.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

Thermal image-based CNN's for ultra-low power people recognition.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

GAP-8: A RISC-V SoC for AI at the Edge of the IoT.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices.
IEEE Trans. VLSI Syst., 2017

Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube.
IEEE Trans. VLSI Syst., 2017

Lightweight Virtual Memory Support for Zero-Copy Sharing of Pointer-Rich Data Structures in Heterogeneous Embedded SoCs.
IEEE Trans. Parallel Distrib. Syst., 2017

A Generic Framework for Modeling MAC Protocols in Wireless Sensor Networks.
IEEE/ACM Trans. Netw., 2017

Accelerated Visual Context Classification on a Low-Power Smartwatch.
IEEE Trans. Human-Machine Systems, 2017

Efficient Virtual Memory Sharing via On-Accelerator Page Table Walking in Heterogeneous Embedded SoCs.
ACM Trans. Embedded Comput. Syst., 2017

Origami: A 803-GOp/s/W Convolutional Network Accelerator.
IEEE Trans. Circuits Syst. Video Techn., 2017

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. on Circuits and Systems, 2017

Kinetic AC/DC Converter for Electromagnetic Energy Harvesting in Autonomous Wearable Devices.
IEEE Trans. on Circuits and Systems, 2017

Smart Energy-Efficient Clock Synthesizer for Duty-Cycled Sensor SoCs in 65 nm/28nm CMOS.
IEEE Trans. on Circuits and Systems, 2017

WARM: Workload-Aware Reliability Management in Linux/Android.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing.
IEEE Trans. Computers, 2017

Energy Analysis of Decoders for Rakeness-Based Compressed Sensing of ECG Signals.
IEEE Trans. Biomed. Circuits and Systems, 2017

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging.
IEEE Trans. Biomed. Circuits and Systems, 2017

A Prosthetic Hand Body Area Controller Based on Efficient Pattern Recognition Control Strategies.
Sensors, 2017

Energy-Efficient Context Aware Power Management with Asynchronous Protocol for Body Sensor Network.
MONET, 2017

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster.
IEEE Micro, 2017

Zeroing for HW-efficient compressed sensing architectures targeting data compression in wireless sensor networks.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster.
J. Solid-State Circuits, 2017

A Sub-mW IoT-Endnode for Always-On Visual Monitoring and Smart Triggering.
IEEE Internet of Things Journal, 2017

Leakage Bounds for Gaussian Side Channels.
IACR Cryptology ePrint Archive, 2017

A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters.
Embedded Systems Letters, 2017

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Design & Test, 2017

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA.
CoRR, 2017

Design Automation for Binarized Neural Networks: A Quantum Leap Opportunity?
CoRR, 2017

An 826 MOPS, 210 uW/MHz Unum ALU in 65 nm.
CoRR, 2017

NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.
CoRR, 2017

A Transprecision Floating-Point Platform for Ultra-Low Power Computing.
CoRR, 2017

Chipmunk: A Systolically Scalable 0.9 mm2, 3.08 Gop/s/mW @ 1.2 mW Accelerator for Near-Sensor Recurrent Neural Network Inference.
CoRR, 2017

Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS.
CoRR, 2017

A sub-mW IoT-endnode for always-on visual monitoring and smart triggering.
CoRR, 2017

CBinfer: Change-Based Inference for Convolutional Neural Networks on Video Data.
CoRR, 2017

Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes.
CoRR, 2017

Soft-to-Hard Vector Quantization for End-to-End Learned Compression of Images and Neural Networks.
CoRR, 2017

Networks on Chips: 15 Years Later.
IEEE Computer, 2017

Prediction horizon vs. efficiency of optimal dynamic thermal control policies in HPC nodes.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

On the Accuracy of Near-Optimal CPU-Based Path Planning for UAVs.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

μDMA: An autonomous I/O subsystem for IoT end-nodes.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Approximate DIV and SQRT instructions for the RISC-V ISA: An efficiency vs. accuracy analysis.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Energy Saving and Thermal Management Opportunities in a Workload-Aware MPI Runtime for a Scientific HPC Computing Node.
Proceedings of the Parallel Computing is Everywhere, 2017

Soft-to-Hard Vector Quantization for End-to-End Learning Compressible Representations.
Proceedings of the Advances in Neural Information Processing Systems 30: Annual Conference on Neural Information Processing Systems 2017, 2017

Towards a Novel HMI Paradigm Based on Mixed EEG and Indoor Localization Platforms.
Proceedings of the New Generation of CAS, 2017

Energy Efficient System for Tactile Data Decoding Using an Ultra-Low Power Parallel Platform.
Proceedings of the New Generation of CAS, 2017

LightProbe: A 64-channel programmable ultrasound transducer head with an integrated front-end and a 26.4 Gb/s optical link.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 142MOPS/mW integrated programmable array accelerator for smart visual processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A wide tuning-range ADFLL for mW-SoCs with dithering-enhanced accuracy in 65 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design of an Energy Aware Petaflops Class High Performance Cluster Based on Power Architecture.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

CAS-CNN: A deep convolutional neural network for image compression artifact suppression.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

CBinfer: Change-Based Inference for Convolutional Neural Networks on Video Data.
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017

GPU-Accelerated Real-Time Path Planning and the Predictable Execution Model.
Proceedings of the International Conference on Computational Science, 2017

Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.
Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, 2017

Deep structured features for semantic segmentation.
Proceedings of the 25th European Signal Processing Conference, 2017

Impact of temporal subsampling on accuracy and performance in practical video classification.
Proceedings of the 25th European Signal Processing Conference, 2017

A multi-sensor and parallel processing SoC for wearable and implantable telemetry systems.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Towards a Mobile Health Platform with Parallel Processing and Multi-sensor Capabilities.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Ultra low-power visual odometry for nano-scale unmanned aerial vehicles.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

WULoRa: An energy efficient IoT end-node for energy harvesting and heterogeneous communication.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A scan-chain based state retention methodology for IoT processors operating on intermittent energy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

GPUguard: Towards supporting a predictable execution model for heterogeneous SoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Continuous learning of HPC infrastructure models using big data analytics and in-memory processing tools.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-to-Information Extraction.
Proceedings of the 54th Annual Design Automation Conference, 2017

Stream Drive: A Dynamic Dataflow Framework For Clustered Embedded Architectures.
Proceedings of the Computing Frontiers Conference, 2017

Self-Sustainability in Nano Unmanned Aerial Vehicles: A Blimp Case Study.
Proceedings of the Computing Frontiers Conference, 2017

Leakage Bounds for Gaussian Side Channels.
Proceedings of the Smart Card Research and Advanced Applications, 2017

A 2.1 μW event-driven wake-up circuit based on a level-crossing ADC for pattern recognition in healthcare.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Optimal Tiling Strategy for Memory Bandwidth Reduction for CNNs.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2017

Benefits in Relaxing the Power Capping Constraint.
Proceedings of the 1st Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, 2017

2016
He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores.
Signal Processing Systems, 2016

PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision.
Signal Processing Systems, 2016

Ekho: A 30.3W, 10k-Channel Fully Digital Integrated 3-D Beamformer for Medical Ultrasound Imaging Achieving 298M Focal Points per Second.
IEEE Trans. VLSI Syst., 2016

A Constraint Programming Scheduler for Heterogeneous High-Performance Computing Machines.
IEEE Trans. Parallel Distrib. Syst., 2016

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement.
ACM Trans. Design Autom. Electr. Syst., 2016

Design, Implementation, and Performance Evaluation of a Flexible Low-Latency Nanowatt Wake-Up Radio Receiver.
IEEE Trans. Industrial Informatics, 2016

Integrated Energy-Aware Management of Supercomputer Hybrid Cooling Systems.
IEEE Trans. Industrial Informatics, 2016

VirtualSoC: A Research Tool for Modern MPSoCs.
ACM Trans. Embedded Comput. Syst., 2016

Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW.
IEEE Trans. Circuits Syst. Video Techn., 2016

Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Hibernus++: A Self-Calibrating and Adaptive System for Transiently-Powered Embedded Devices.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Graceful Performance Modulation for Power-Neutral Transient Computing Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software.
Proceedings of the IEEE, 2016

Controlling NUMA effects in embedded manycore applications with lightweight nested parallelism support.
Parallel Computing, 2016

Associative Memristive Memory for Approximate Computing in GPUs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

CIRCA-GPUs: Increasing Instruction Reuse Through Inexact Computing in GP-GPUs.
IEEE Design & Test, 2016

Deep Structured Features for Semantic Segmentation.
CoRR, 2016

A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices.
CoRR, 2016

CAS-CNN: A Deep Convolutional Neural Network for Image Compression Artifact Suppression.
CoRR, 2016

Computationally Efficient Target Classification in Multispectral Image Data with Deep Neural Networks.
CoRR, 2016

YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights.
CoRR, 2016

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
CoRR, 2016

Predictive Modeling for Job Power Consumption in HPC Systems.
Proceedings of the High Performance Computing - 31st International Conference, 2016

A Dual Processor Energy-Efficient Platform with Multi-core Accelerator for Smart Sensing.
Proceedings of the Sensor Systems and Software - 7th International Conference, S-Cube 2016, 2016

SHelmet: An Intelligent Self-sustaining Multi Sensors Smart Helmet for Bikers.
Proceedings of the Sensor Systems and Software - 7th International Conference, S-Cube 2016, 2016

SNW-MAC: An Asynchronous Protocol Leveraging Wake-Up Receivers for Data Gathering in Star Networks.
Proceedings of the Sensor Systems and Software - 7th International Conference, S-Cube 2016, 2016

A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Autonomous smartwatch with flexible sensors for accurate and continuous mapping of skin temperature.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Energy-efficient design of an always-on smart visual trigger.
Proceedings of the IEEE International Smart Cities Conference, 2016

Poster Abstract: KinetiSee - A Perpetual Wearable Camera Acquisition System with a Kinetic Harvester.
Proceedings of the 15th ACM/IEEE International Conference on Information Processing in Sensor Networks, 2016

Poster Abstract: An Ultra-Low Power Wake up Radio with Addressing and Retransmission Capabilities for Advanced Energy Efficient MAC Protocols.
Proceedings of the 15th ACM/IEEE International Conference on Information Processing in Sensor Networks, 2016

Poster Abstract: MagoNode++ - A Wake-Up-Radio-Enabled Wireless Sensor Mote for Energy-Neutral Applications.
Proceedings of the 15th ACM/IEEE International Conference on Information Processing in Sensor Networks, 2016

Poster Abstract: Wake-Up Receivers for Energy Efficient and Low Latency Communication.
Proceedings of the 15th ACM/IEEE International Conference on Information Processing in Sensor Networks, 2016

Evaluation of synchronization protocols for fine-grain HPC sensor data time-stamping and collection.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Cooling-aware node-level task allocation for next-generation green HPC systems.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Thermal model identification of supercomputing nodes in production environment.
Proceedings of the IECON 2016, 2016

Hyperdimensional biosignal processing: A case study for EMG-based hand gesture recognition.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Always-on motion detection with application-level error control on a near-threshold approximate computing platform.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

VarDroid: Online Variability Emulation in Android/Linux Platforms.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Analytical and Experimental Evaluation of Wake-Up Receivers Based Protocols.
Proceedings of the 2016 IEEE Global Communications Conference, 2016

Lightweight IO Virtualization On MPU Enabled Microcontrollers.
Proceedings of the Embedded Operating Systems Workshop co-located with the Embedded Systems Week (ESWEEK 2016), 2016

Mobile Ultrasound Imaging on Heterogeneous Multi-Core Platforms.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016

A 2 MS/s 10A Hall current sensor SoC with digital compressive sensing encoder in 0.16 µm BCD.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Context Change Detection for an Ultra-Low Power Low-Resolution Ego-Vision Imager.
Proceedings of the Computer Vision - ECCV 2016 Workshops, 2016

DARDIS: Distributed And Randomized DIspatching and Scheduling.
Proceedings of the ECAI 2016 - 22nd European Conference on Artificial Intelligence, 29 August-2 September 2016, The Hague, The Netherlands, 2016

A Low Latency and Energy Efficient Communication Architecture for Heterogeneous Long-Short Range Communication.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

High-efficiency logarithmic number unit design based on an improved cotransformation scheme.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Towards near-threshold server processors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Low-power multichannel spectro-temporal feature extraction circuit for audio pattern wake-up.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Dynamic energy burst scaling for transiently powered systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

An optimized task-based runtime system for resource-constrained parallel accelerators.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Quantifying the benefits of compressed sensing on a WBSN-based real-time biosignal monitor.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

An energy-efficient parallel algorithm for real-time near-optimal UAV path planning.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

PHIDIAS: ultra-low-power holistic design for smart bio-signals computing platforms.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Sub-PicoJoule per operation scalable computing: why, when, how?
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Enabling OpenVX support in mW-scale parallel accelerators.
Proceedings of the 2016 International Conference on Compilers, 2016

Application of compressed sensing to ECG signals: Decoder-side benefits of the rakeness approach.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

Sampling modulation: An energy efficient novel feature extraction for biosignal processing.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

Scalable EEG seizure detection on an ultra low power multi-core architecture.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

A Contactless, Energy-Neutral Power Meter for Smart City Applications.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2016

Long-Range Radio for Underground Sensors in Geothermal Energy Systems.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2016

DARDIS: Distributed And Randomized DIspatching and Scheduling.
Proceedings of the AI*IA 2016: Advances in Artificial Intelligence - XVth International Conference of the Italian Association for Artificial Intelligence, Genova, Italy, November 29, 2016

2015
Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory.
IEEE Trans. VLSI Syst., 2015

A Modular Shared L2 Memory Design for 3-D Integration.
IEEE Trans. VLSI Syst., 2015

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms.
IEEE Trans. Parallel Distrib. Syst., 2015

Simplifying Many-Core-Based Heterogeneous SoC Programming With Offload Directives.
IEEE Trans. Industrial Informatics, 2015

Guaranteed Computational Resprinting via Model-Predictive Control.
ACM Trans. Embedded Comput. Syst., 2015

3D CV Descriptor on Parallel Heterogeneous Platforms.
ACM Trans. Embedded Comput. Syst., 2015

A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation.
IEEE Trans. on Circuits and Systems, 2015

A Low-Power Architecture for Punctured Compressed Sensing and Estimation in Wireless Sensor-Nodes.
IEEE Trans. on Circuits and Systems, 2015

Energy-Efficiency Analysis of Analog and Digital Compressive Sensing in Wireless Sensors.
IEEE Trans. on Circuits and Systems, 2015

Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators.
IEEE Trans. Computers, 2015

A Versatile Embedded Platform for EMG Acquisition and Gesture Recognition.
IEEE Trans. Biomed. Circuits and Systems, 2015

Aging-Aware Compilation for GP-GPUs.
TACO, 2015

Sub-Sampling Framework Comparison for Low-Power Data Gathering: A Comparative Analysis.
Sensors, 2015

Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level.
Integration, 2015

Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems.
Embedded Systems Letters, 2015

Origami: A Convolutional Network Accelerator.
CoRR, 2015

A 2.4 GHz-868 MHz dual-band wake-up radio for wireless sensor network and IoT.
Proceedings of the 11th IEEE International Conference on Wireless and Mobile Computing, 2015

Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Automatic multiview synthesis - Prototype demo.
Proceedings of the 2015 Visual Communications and Image Processing, 2015

Automatic multiview synthesis - Towards a mobile system on a chip.
Proceedings of the 2015 Visual Communications and Image Processing, 2015

A framework for optimizing OpenVX applications performance on embedded manycore accelerators.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Experimental evaluation of a sEMG-based human-robot interface for human-like grasping tasks.
Proceedings of the 2015 IEEE International Conference on Robotics and Biomimetics, 2015

Long-Term ECG monitoring with zeroing Compressed Sensing approach.
Proceedings of the Nordic Circuits and Systems Conference, 2015

An Energy Neutral Wearable Camera with EPD Display.
Proceedings of the 2015 workshop on Wearable Systems and Applications, 2015

ADRENALINE: An OpenVX Environment to Optimize Embedded Vision Applications on Many-core Accelerators.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Enabling Scalable and Fine-Grained Nested Parallelism on Embedded Many-cores.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Energy-Aware Bio-signal Compressed Sensing Reconstruction: FOCUSS on the WBSN-Gateway.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Synergistic Architecture and Programming Model Support for Approximate Micropower Computing.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Message from the general chairs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Ultra-Low Power Context Recognition Fusing Sensor Data from an Energy-Neutral Smart Watch.
Proceedings of the Internet of Things. IoT Infrastructures, 2015

Beyond duty cycling: Wake-up radio with selective awakenings for long-lived wireless sensing systems.
Proceedings of the 2015 IEEE Conference on Computer Communications, 2015

Exploring architectural heterogeneity in intelligent vision systems.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

PULP: A parallel ultra low power platform for next generation IoT applications.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Origami: A Convolutional Network Accelerator.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Extending Body Sensor Nodes' Lifetime Using a Wearable Wake-up Radio.
Proceedings of the Future Access Enablers for Ubiquitous and Intelligent Infrastructures, 2015

Context Aware Power Management Enhanced by Radio Wake Up in Body Area Networks.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

Digitally controlled feedback for DC offset cancellation in a wearable multichannel EMG platform.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Approximate associative memristive memory for energy-efficient GPUs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Tackling the bottleneck of delay tables in 3D ultrasound imaging.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Paper, pen and ink: an innovative system and software framework to assist writing rehabilitation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Reducing energy consumption in microcontroller-based platforms with low design margin co-processors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Energy-aware cooling for hot-water cooled supercomputers.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

An ultra-low power dual-mode ECG monitor for healthcare and wellness.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

High performance AXI-4.0 based interconnect for extensible smart memory cubes.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Accelerating real-time embedded scene labeling with convolutional networks.
Proceedings of the 52nd Annual Design Automation Conference, 2015

ANTAREX - AutoTuning and Adaptivity appRoach for Energy Efficient eXascale HPC Systems.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

Power Capping in High Performance Computing Systems.
Proceedings of the Principles and Practice of Constraint Programming, 2015

Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

An Evaluation of Memory Sharing Performance for Heterogeneous Embedded SoCs with Many-Core Accelerators.
Proceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores, 2015

Runtime Support for Multiple Offload-Based Programming Models on Embedded Manycore Accelerators.
Proceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores, 2015

Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Multiple Biopotentials Acquisition System for Wearable Applications.
Proceedings of the BIODEVICES 2015, 2015

Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

A Smart LED Light Control System for Environmentally Friendly Buildings.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2015

Sensormind: Virtual Sensing and Complex Event Detection for Internet of Things.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2015

A CP Scheduler for High-Performance Computers.
Proceedings of the Doctoral Consortium (DC) co-located with the 14th Conference of the Italian Association for Artificial Intelligence (AI*IA 2015), 2015

2014
A Novel Object-Oriented Software Cache for Scratchpad-Based Multi-Core Clusters.
Signal Processing Systems, 2014

Ensuring Survivability of Resource-Intensive Sensor Networks Through Ultra-Low Power Overlays.
IEEE Trans. Industrial Informatics, 2014

Compressive Sensing Optimization for Signal Ensembles in WSNs.
IEEE Trans. Industrial Informatics, 2014

Extended Wireless Monitoring Through Intelligent Hybrid Energy Supply.
IEEE Trans. Industrial Electronics, 2014

Bias-Compensated Least Squares Identification of Distributed Thermal Models for Many-Core Systems-on-Chip.
IEEE Trans. on Circuits and Systems, 2014

Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability.
IEEE Trans. Computers, 2014

At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs.
IEEE Trans. Computers, 2014

An Effective Gray-Box Identification Procedure for Multicore Thermal Modeling.
IEEE Trans. Computers, 2014

Clamp-and-Forget: A self-sustainable non-invasive wireless sensor node for smart metering applications.
Microelectronics Journal, 2014

A low power wireless node for contact and contactless heart monitoring.
Microelectronics Journal, 2014

An ultra-low power resilient multi-core architecture with static and dynamic tolerance to ambient temperature-induced variability.
Microprocessors and Microsystems - Embedded Hardware Design, 2014

Message Passing-Aware Power Management on Many-Core Systems.
J. Low Power Electronics, 2014

Sleep power minimisation using adaptive duty-cycling of DC-DC converters in state-retentive systems.
IET Circuits, Devices & Systems, 2014

Improving Resilience to Timing Errors by Exposing Variability Effects to Software in Tightly-Coupled Processor Clusters.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

CROSS cyclic resource-constrained scheduling solver.
Artif. Intell., 2014

An ultra low power high sensitivity wake-up radio receiver with addressing capability.
Proceedings of the IEEE 10th International Conference on Wireless and Mobile Computing, 2014

Optimized active and power-down mode refresh control in 3D-DRAMs.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Energy-efficient vision on the PULP platform for ultra-low power parallel computing.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Speculative synchronization for coherence-free embedded NUMA architectures.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Towards EMG control interface for smart garments.
Proceedings of the ISWC'14, 2014

Quantifying the impact of variability on the energy efficiency for a next-generation ultra-green supercomputer.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Approximate compressed sensing: ultra-low power biosignal processing via aggressive voltage scaling on a hybrid memory multi-core processor.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

An architecture for low-power compressed sensing and estimation in wireless sensor nodes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A Virtualization Framework for IOMMU-less Many-Core Accelerators.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

A high-sensitivity fully passive wake-up radio front-end for wireless sensor nodes.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

Dynamic variability management in mobile multicore processors under lifetime constraints.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Optimum: Thermal-aware task allocation for heterogeneous many-core devices.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

InfiniTime: A multi-sensor energy neutral wearable bracelet.
Proceedings of the International Green Computing Conference, 2014

Efficient parallel beamforming for 3D ultrasound imaging.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

He-P2012: architectural heterogeneity exploration on a scalable many-core platform.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

An On-line Reliability Emulation Framework.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Temporal memoization for energy-efficient timing error recovery in GPGPUs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A Linux-governor based Dynamic Reliability Manager for android mobile devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Context aware power management for motion-sensing body area network nodes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Unveiling Eurora - Thermal and power characterization of the most energy-efficient supercomputer in the world.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Optimizing memory bandwidth in OpenVX graph execution on embedded many-core accelerators.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

0, 1, 2, many - A classroom occupancy monitoring system for smart public buildings.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Rakeness-based compressed sensing on ultra-low power multi-core biomedicai processors.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Gesture Recognition in Ego-centric Videos Using Dense Trajectories and Hand Segmentation.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2014

Brain-Inspired Classroom Occupancy Monitoring on a Low-Power Mobile Platform.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2014

Supporting localized OpenVX kernel execution for efficient computer vision application development on STHORM many-core platform.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

Analysis of Robust Implementation of an EMG Pattern Recognition based Control.
Proceedings of the BIOSIGNALS 2014, 2014

Assessing the area/power/performance tradeoffs for an integrated fully-digital, large-scale 3D-ultrasound beamformer.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

EMG-based hand gesture recognition with flexible analog front end.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Exploring DMA-assisted prefetching strategies for software caches on multicore clusters.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

He-P2012: Architectural heterogeneity exploration on a scalable many-core platform.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Aging-Aware Energy-Efficient Workload Allocation for Mobile Multimedia Platforms.
IEEE Trans. Parallel Distrib. Syst., 2013

Thermal and Energy Management of High-Performance Multicores: Distributed and Self-Calibrating Model-Predictive Controller.
IEEE Trans. Parallel Distrib. Syst., 2013

Designing best effort networks-on-chip to meet hard latency constraints.
ACM Trans. Embedded Comput. Syst., 2013

Spatial Memoization: Concurrent Instruction Reuse to Correct Timing Errors in SIMD Architectures.
IEEE Trans. on Circuits and Systems, 2013

Exploration and Optimization of 3-D Integrated DRAM Subsystems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip.
IEEE Trans. Computers, 2013

Robust Scheduling of Task Graphs under Execution Time Uncertainty.
IEEE Trans. Computers, 2013

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores.
Parallel Computing, 2013

Maximum-throughput mapping of SDFGs on multi-core SoC platforms.
J. Parallel Distrib. Comput., 2013

A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects.
IET Computers & Digital Techniques, 2013

Multimodal Video Analysis on Self-Powered Resource-Limited Wireless Smart Camera.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

SIMinG-1k: A thousand-core simulator running on general-purpose graphical processing units.
Concurrency and Computation: Practice and Experience, 2013

Wearable low power dry surface wireless sensor node for healthcare monitoring application.
Proceedings of the 9th IEEE International Conference on Wireless and Mobile Computing, 2013

A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

SWIFTNET: A data acquisition protocol for fast-reactive monitoring applications.
Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, 2013

Heterogeneous multi-harvester for wireless sensor networks.
Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013

Improving the efficiency of air-flow energy harvesters combining active and passive rectifiers.
Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013

Powering wireless sensor nodes with micro fuel cells.
Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013

Power saving policies for multipurpose WBAN.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A variation tolerant architecture for ultra low power multi-processor cluster.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

On-line thermal emulation: How to speed-up your thermal controller design.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Efficient energy management and data recovery in sensor networks using latent variables based tensor factorization.
Proceedings of the 16th ACM International Conference on Modeling, 2013

Prolonging the lifetime of wireless sensor networks using light-weight forecasting algorithms.
Proceedings of the 2013 IEEE Eighth International Conference on Intelligent Sensors, 2013

Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

VirtualSoC: A Full-System Simulation Environment for Massively Parallel Heterogeneous System-on-Chip.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Low-power wireless accelerometer-based system for wear detection of bandsaw blades.
Proceedings of the 11th IEEE International Conference on Industrial Informatics, 2013

A power-aware multi harvester power unit with hydrogen fuel cell for embedded systems in outdoor applications.
Proceedings of the International Green Computing Conference, 2013

An Ambient Temperature Variation Tolerance Scheme for an Ultra Low Power Shared-L1 Processor Cluster.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

An Application-Specific Forecasting Algorithm for Extending WSN Lifetime.
Proceedings of the IEEE International Conference on Distributed Computing in Sensor Systems, 2013

Trade-offs of Forecasting Algorithm for Extending WSN Lifetime in a Real-World Deployment.
Proceedings of the IEEE International Conference on Distributed Computing in Sensor Systems, 2013

A survey of multi-source energy harvesting systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Variation-tolerant OpenMP tasking on tightly-coupled processor clusters.
Proceedings of the Design, Automation and Test in Europe, 2013

Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging.
Proceedings of the Design, Automation and Test in Europe, 2013

Design of an ultra-low power device for aircraft structural health monitoring.
Proceedings of the Design, Automation and Test in Europe, 2013

SCC thermal model identification via advanced bias-compensated least-squares.
Proceedings of the Design, Automation and Test in Europe, 2013

Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters.
Proceedings of the Design, Automation and Test in Europe, 2013

Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Aging-aware compiler-directed VLIW assignment for GPGPU architectures.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Workload and user experience-aware dynamic reliability management in multicore processors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

GPU-SHOT: Parallel Optimization for Real-Time 3D Local Description.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2013

A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

A shared-FPU architecture for ultra-low power MPSoCs.
Proceedings of the Computing Frontiers Conference, 2013

Identification of many-core systems-on-chip with input and output noises.
Proceedings of the 52nd IEEE Conference on Decision and Control, 2013

Synchronization methods for Bluetooth based WBANs.
Proceedings of the 2013 IEEE International Conference on Body Sensor Networks, 2013

A highly efficient, thread-safe software cache implementation for tightly-coupled multicore clusters.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Combination of hybrid energy harvesters with MEMS piezoelectric and nano-Watt radio wake up to extend lifetime of system for wireless sensor nodes.
Proceedings of the ARCS 2013, 2013

A Multi Harvester with Hydrogen Fuel Cell for Outdoor Applications.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2013

HapticLib: a haptic feedback library for embedded platforms.
Proceedings of the ACM Symposium on Applied Perception 2013, 2013

A high-performance multiported L2 memory IP for scalable three-dimensional integration.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Online thermal control methods for multiprocessor systems.
ACM Trans. Design Autom. Electr. Syst., 2012

Distributed Compressive Sampling for Lifetime Optimization in Dense Wireless Sensor Networks.
IEEE Trans. Industrial Informatics, 2012

Network-Level Power-Performance Trade-Off in Wearable Activity Recognition: A Dynamic Sensor Selection Approach.
ACM Trans. Embedded Comput. Syst., 2012

Variability-tolerant workload allocation for MPSoC energy minimization under real-time constraints.
ACM Trans. Embedded Comput. Syst., 2012

Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters.
IEEE Trans. on Circuits and Systems, 2012

Robust Near-Threshold Design With Fine-Grained Performance Tunability.
IEEE Trans. on Circuits and Systems, 2012

Variability-Aware Task Allocation for Energy-Efficient Quality of Service Provisioning in Embedded Streaming Multimedia Applications.
IEEE Trans. Computers, 2012

An OpenMP Compiler for Efficient Use of Distributed Scratchpad Memory in MPSoCs.
IEEE Trans. Computers, 2012

Reconfigurable natural interaction in smart environments: approach and prototype implementation.
Personal and Ubiquitous Computing, 2012

Row-based FBB: A design-time optimization for post-silicon tunable circuits.
Microelectronics Journal, 2012

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands.
J. Electrical and Computer Engineering, 2012

Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience.
IJERTCS, 2012

Low-power processor architecture exploration for online biomedical signal analysis.
IET Circuits, Devices & Systems, 2012

A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memory.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Configurable Low-Latency Interconnect for Multi-core Clusters.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Opportunistic hierarchical classification for power optimization in wearable movement monitoring systems.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

A tightly-coupled multi-core cluster with shared-memory HW accelerators.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Combined methods to extend the lifetime of power hungry WSN with multimodal sensors and nanopower wakeups.
Proceedings of the 8th International Wireless Communications and Mobile Computing Conference, 2012

A multi-banked shared-l1 cache architecture for tightly coupled processor clusters.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Characterization of lithium-ion capacitors for low-power energy neutral wireless sensor networks.
Proceedings of the Ninth International Conference on Networked Sensing, 2012

Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chip.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

An energy efficient DRAM subsystem for 3D integrated SoCs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Analysis of instruction-level vulnerability to dynamic voltage and temperature variations.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Fast and lightweight support for nested parallelism on cluster-based embedded many-cores.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Smart power unit with ultra low power radio trigger capabilities for wireless sensor networks.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A resilient architecture for low latency communication in shared-L1 processor clusters.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Global Cyclic Cumulative Constraint.
Proceedings of the Integration of AI and OR Techniques in Contraint Programming for Combinatorial Optimzation Problems, 2012

Don't burn your mobile!: safe computational re-sprinting via model predictive control.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

A distributed interleaving scheme for efficient access to WideIO DRAM memory.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Full system simulation of many-core heterogeneous SoCs using GPU and QEMU semihosting.
Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units, 2012

Design and validation of an attitude and heading reference system for an aerial robot prototype.
Proceedings of the American Control Conference, 2012

Optimization and Controlled Systems: A Case Study on Thermal Aware Workload Dispatching.
Proceedings of the Twenty-Sixth AAAI Conference on Artificial Intelligence, 2012

2011
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.
IEEE Trans. VLSI Syst., 2011

Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating.
IEEE Trans. VLSI Syst., 2011

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2010.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Supporting OpenMP on a multi-cluster embedded MPSoC.
Microprocessors and Microsystems - Embedded Hardware Design, 2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
J. Solid-State Circuits, 2011

Parallel Rendering and Animation of Subdivision Surfaces on the Cell BE Processor.
International Journal of Parallel Programming, 2011

Variability compensation for full-swing against low-swing on-chip communication.
IET Computers & Digital Techniques, 2011

Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Optimal resource allocation and scheduling for the CELL BE platform.
Annals OR, 2011

Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip.
Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011

Merging RFID, visual and gesture recognition technologies to generate and manage smart environments.
Proceedings of the 2011 IEEE International Conference on RFID-Technologies and Applications, 2011

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

A System Level Approach to Multi-core Thermal Sensors Calibration.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

A distributed and topology-agnostic approach for on-line NoC testing.
Proceedings of the NOCS 2011, 2011

SCC Thermal Sensor Characterization and Calibration.
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011

A DRAM Centric NoC Architecture and Topology Design Approach.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Simulation Based Buffer Sizing Algorithm for Network on Chips.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Method for Integrating Network-on-Chip Topologies with 3D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Moonrake chip - GALS demonstrator in 40 nm CMOS technology.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Exploring instruction caching strategies for tightly-coupled shared-memory clusters.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Thermal-aware system-level modeling and management for Multi-Processor Systems-on-Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Static Thermal Model Learning for High-Performance Multicore Servers.
Proceedings of 20th International Conference on Computer Communications and Networks, 2011

PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status.
Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011

Design space exploration for 3D-stacked DRAMs.
Proceedings of the Design, Automation and Test in Europe, 2011

A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters.
Proceedings of the Design, Automation and Test in Europe, 2011

An efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platforms.
Proceedings of the Design, Automation and Test in Europe, 2011

ReliNoC: A reliable network for priority-based on-chip communication.
Proceedings of the Design, Automation and Test in Europe, 2011

An effective multi-source energy harvester for low power applications.
Proceedings of the Design, Automation and Test in Europe, 2011

A distributed and self-calibrating model-predictive controller for energy and thermal management of high-performance multicores.
Proceedings of the Design, Automation and Test in Europe, 2011

Precedence Constraint Posting for Cyclic Scheduling Problems.
Proceedings of the Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, 2011

A Constraint Based Approach to Cyclic RCPSP.
Proceedings of the Principles and Practice of Constraint Programming - CP 2011, 2011

Neuron Constraints to Model Complex Real-World Problems.
Proceedings of the Principles and Practice of Constraint Programming - CP 2011, 2011

SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

MPOpt-Cell: a high-performance data-flow programming environment for the CELL BE processor.
Proceedings of the 8th Conference on Computing Frontiers, 2011

GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms.
Proceedings of the 11th IEEE/ACM International Symposium on Cluster, 2011

A Cost-effective Indoor Vibrotactile Navigation System for the Blind.
Proceedings of the HEALTHINF 2011, 2011

Energy-aware objects abandon / removal detection.
Proceedings of the 8th IEEE International Conference on Advanced Video and Signal-Based Surveillance, 2011

Synchronous Reactive Fine Grain Tasks Management for Homogeneous Many-Core Architectures.
Proceedings of the ARCS 2011, 2011

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks.
IEEE Trans. VLSI Syst., 2010

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands.
IEEE Trans. on Circuits and Systems, 2010

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Adaptive Power Management for Environmentally Powered Systems.
IEEE Trans. Computers, 2010

Stochastic allocation and scheduling for conditional task graphs in multi-processor systems-on-chip.
J. Scheduling, 2010

Capacitance DNA bio-chips improved by new probe immobilization strategies.
Microelectronics Journal, 2010

Comparison of energy intake prediction algorithms for systems powered by photovoltaic harvesters.
Microelectronics Journal, 2010

Accelerometer-based fall detection using optimized ZigBee data streaming.
Microelectronics Journal, 2010

A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.
J. Low Power Electronics, 2010

Collecting Datasets from Ambient Intelligence Environments.
IJACI, 2010

Energy aware multimodal embedded video surveillance.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Compressive sensing optimization over ZigBee networks.
Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010

GENESI: Green sEnsor NEtworks for Structural monItoring.
Proceedings of the Seventh Annual IEEE Communications Society Conference on Sensor, 2010

A kinetic energy harvester with fast start-up for wearable body-monitoring sensors.
Proceedings of the 4th International Conference on Pervasive Computing Technologies for Healthcare, 2010

Wearable assistant for load monitoring: recognition of on - body load placement from gait alterations.
Proceedings of the 4th International Conference on Pervasive Computing Technologies for Healthcare, 2010

Automatic synthesis of near-threshold circuits with fine-grained performance tunability.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Rapid and efficient application design using a signal processing framework for WSN.
Proceedings of the 15th IEEE Symposium on Computers and Communications, 2010

3D NoCs - Unifying inter & intra chip communication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Scalable instruction set simulator for thousand-core architectures running on GPGPUs.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010

Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems.
Proceedings of the 28th International Conference on Computer Design, 2010

A new physical routing approach for robust bundled signaling on NoC links.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Energy Efficient Cooperative Multimodal Ambient Monitoring.
Proceedings of the Smart Sensing and Context - 5th European Conference, 2010

Evaluating OpenMP Support Costs on MPSoCs.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

A method to remove deadlocks in Networks-on-Chips with Wormhole flow control.
Proceedings of the Design, Automation and Test in Europe, 2010

Efficient OpenMP data mapping for multicore platforms with vertically stacked memory.
Proceedings of the Design, Automation and Test in Europe, 2010

Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs.
Proceedings of the Design, Automation and Test in Europe, 2010

An efficient distributed memory interface for many-core platform with 3D stacked DRAM.
Proceedings of the Design, Automation and Test in Europe, 2010

Parallel subdivision surface rendering and animation on the Cell BE processor.
Proceedings of the Design, Automation and Test in Europe, 2010

An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms.
Proceedings of the Design, Automation and Test in Europe, 2010

Networks on Chips: from research to products.
Proceedings of the 47th Design Automation Conference, 2010

Exploring programming model-driven QoS support for NoC-based platforms.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Variability-tolerant run-time workload allocation for MPSoC energy minimization under real-time constraints.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Vertical stealing: robust, locality-aware do-all workload distribution for 3D MPSoCs.
Proceedings of the 2010 International Conference on Compilers, 2010

Battery-aware power management techniques for wearable haptic nodes.
Proceedings of the 5th International ICST Conference on Body Area Networks, 2010

Methods for Designing Reliable Probe Arrays.
Proceedings of the 10th IEEE International Conference on Bioinformatics and Bioengineering, 2010

Design of networks on chips for 3D ICs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits.
IEEE Trans. on Circuits and Systems, 2009

Design of a Solar-Harvesting Circuit for Batteryless Embedded Systems.
IEEE Trans. on Circuits and Systems, 2009

Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Thermal Balancing Policy for Multiprocessor Stream Computing Platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

A Feedback-Based Approach to DVFS in Data-Flow Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Photovoltaic scavenging systems: Modeling and optimization.
Microelectronics Journal, 2009

Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating.
J. Low Power Electronics, 2009

Hidden Markov Model based gesture recognition on low-cost, low-power Tangible User Interfaces.
Entertainment Computing, 2009

OpenMP Support for NBTI-Induced Aging Tolerance in MPSoCs.
Proceedings of the Stabilization, 2009

A floorplan-aware interactive tool flow for NoC design and synthesis.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A wireless system for gait and posture analysis based on pressure insoles and Inertial Measurement Units.
Proceedings of the 3rd International Conference on Pervasive Computing Technologies for Healthcare, 2009

Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Load Optimization of an Inductive Power Link for Remote Powering of Biomedical Implants.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Hidden Markov Models Implementation for Tangible Interfaces.
Proceedings of the Intelligent Technologies for Interactive Entertainment, 2009

Adaptive power control for solar harvesting multimodal wireless smart camera.
Proceedings of the Third ACM/IEEE International Conference on Distributed Smart Cameras, 2009

A method for calculating hard QoS guarantees for Networks-on-Chip.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Variability-tolerant workload allocation for MPSoC energy minimization under real-time constraints.
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

HVS-DBS: human visual system-aware dynamic luminance backlight scaling for video streaming applications.
Proceedings of the 9th ACM & IEEE International conference on Embedded software, 2009

SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips.
Proceedings of the Design, Automation and Test in Europe, 2009

Physically clustered forward body biasing for variability compensation in nanometer CMOS design.
Proceedings of the Design, Automation and Test in Europe, 2009

Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip.
Proceedings of the Design, Automation and Test in Europe, 2009

Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels.
Proceedings of the Design, Automation and Test in Europe, 2009

Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy.
Proceedings of the Design, Automation and Test in Europe, 2009

Robust non-preemptive hard real-time scheduling for clustered multicore platforms.
Proceedings of the Design, Automation and Test in Europe, 2009

Synthesis of low-overhead configurable source routing tables for network interfaces.
Proceedings of the Design, Automation and Test in Europe, 2009

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications.
Proceedings of the Design, Automation and Test in Europe, 2009

Visual quality analysis for dynamic backlight scaling in LCD systems.
Proceedings of the Design, Automation and Test in Europe, 2009

NoC topology synthesis for supporting shutdown of voltage islands in SoCs.
Proceedings of the 46th Design Automation Conference, 2009

Throughput Constraint for Synchronous Data Flow Graphs.
Proceedings of the Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, 2009

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints.
Proceedings of the 2009 International Conference on Complex, 2009

Predictability vs. Efficiency in the Multicore Era: Fight of Titans or Happy Ever after?.
Proceedings of the Computer Aided Verification, 21st International Conference, 2009

Multimodal Abandoned/Removed Object Detection for Low Power Video Surveillance Systems.
Proceedings of the Sixth IEEE International Conference on Advanced Video and Signal Based Surveillance, 2009

Synthesis of networks on chips for 3D systems on chips.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip.
Proceedings of the Embedded Systems Design and Verification, 2009

SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs.
Proceedings of the Embedded Systems Design and Verification, 2009

2008
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.
IEEE Trans. VLSI Syst., 2008

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration.
ACM Trans. Design Autom. Electr. Syst., 2008

Modeling and Optimization of a Solar Energy Harvester System for Self-Powered Wireless Sensor Networks.
IEEE Trans. Industrial Electronics, 2008

A Reactive and Cycle-True IP Emulator for MPSoC Exploration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Interfacing human and computer with wireless body area sensor networks: the WiMoCA solution.
Multimedia Tools Appl., 2008

Network-on-Chip design and synthesis outlook.
Integration, 2008

A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness.
International Journal of Parallel Programming, 2008

Exploring architectural solutions for energy optimisations in bus-based system-on-chip.
IET Computers & Digital Techniques, 2008

The State of ESL Design [Roundtable].
IEEE Design & Test of Computers, 2008

Joint co-clustering: Co-clustering of genomic and clinical bioimaging data.
Computers & Mathematics with Applications, 2008

TOM: enhancement and extension of a tool suite for in silico approaches to multigenic hereditary disorders.
Bioinformatics, 2008

A smart wireless glove for gesture interaction.
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2008

Validation of a wireless portable biofeedback system for balance control: Preliminary results.
Proceedings of the 2nd International ICST Conference on Pervasive Computing Technologies for Healthcare, 2008

Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A High-Performance Wireless Sensor Node for Industrial Control Applications.
Proceedings of the Third International Conference on Systems, 2008

Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming.
Proceedings of the Logic Programming, 24th International Conference, 2008

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Approximate Control Design for Solar Driven Sensor Nodes.
Proceedings of the Hybrid Systems: Computation and Control, 11th International Workshop, 2008

Optimal sleep transistor synthesis under timing and area constraints.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Activity Recognition from On-Body Sensors: Accuracy-Power Trade-Off by Dynamic Sensor Selection.
Proceedings of the Wireless Sensor Networks, 5th European Conference, 2008

Analysis of Audio Streaming Capability of Zigbee Networks.
Proceedings of the Wireless Sensor Networks, 5th European Conference, 2008

DBS4video: dynamic luminance backlight scaling based on multi-histogram frame characterization for video streaming application.
Proceedings of the 8th ACM & IEEE International conference on Embedded software, 2008

Cellflow: A Parallel Application Development Environment with Run-Time Support for the Cell BE Processor.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

A Solar-powered Video Sensor Node for Energy Efficient Multimodal Surveillance.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.
Proceedings of the Design, Automation and Test in Europe, 2008

A Scalable Algorithmic Framework for Row-Based Power-Gating.
Proceedings of the Design, Automation and Test in Europe, 2008

Serialized Asynchronous Links for NoC.
Proceedings of the Design, Automation and Test in Europe, 2008

Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization.
Proceedings of the Design, Automation and Test in Europe, 2008

Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008

Robust and Low Complexity Rate Control for Solar Powered Sensors.
Proceedings of the Design, Automation and Test in Europe, 2008

Developing Mesochronous Synchronizers to Enable 3D NoCs.
Proceedings of the Design, Automation and Test in Europe, 2008

Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints.
Proceedings of the Design, Automation and Test in Europe, 2008

An Efficient Solar Energy Harvester for Wireless Sensor Nodes.
Proceedings of the Design, Automation and Test in Europe, 2008

HOT TOPIC - 3D Integration or How to Scale in the 21st Century.
Proceedings of the Design, Automation and Test in Europe, 2008

Multi-stage Benders Decomposition for Optimizing Multicore Architectures.
Proceedings of the Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, 2008

A Constraint Programming Approach for Allocation and Scheduling on the CELL Broadband Engine.
Proceedings of the Principles and Practice of Constraint Programming, 2008

Evolving tuis with smart objects for multi-context interaction.
Proceedings of the Extended Abstracts Proceedings of the 2008 Conference on Human Factors in Computing Systems, 2008

MM-Correction: Meta-analysis-Based Multiple Hypotheses Correction in Omic Studies.
Proceedings of the Biomedical Engineering Systems and Technologies, 2008

Statistical Significance in Omic Data Analyses - Alternative/Complementary Method for Efficient Automatic Identification of Statistically Significant Tests in High Throughput Biological Studies.
Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008

Reliability-aware design for nanometer-scale devices.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees.
VLSI Design, 2007

Area and Power Modeling for Networks-on-Chip with Layout Awareness.
VLSI Design, 2007

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2007

HW-SW emulation framework for temperature-aware design in MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2007

Co-clustering: A Versatile Tool for Data Analysis in Biomedical Informatics.
IEEE Trans. Information Technology in Biomedicine, 2007

Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology.
Trans. HiPEAC, 2007

Power macromodeling of MPSoC message passing primitives.
ACM Trans. Embedded Comput. Syst., 2007

A control theoretic approach to energy-efficient pipelined computation in MPSoCs.
ACM Trans. Embedded Comput. Syst., 2007

Timing-Error-Tolerant Network-on-Chip Design Methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

An Application-Specific Design Methodology for On-Chip Crossbar Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support.
IEEE Trans. Computers, 2007

A hardware/software framework for supporting transactional memory in a MPSoC environment.
SIGARCH Computer Architecture News, 2007

Real-time scheduling for energy harvesting sensor nodes.
Real-Time Systems, 2007

Bringing NoCs to 65 nm.
IEEE Micro, 2007

A low-power wireless video sensor node for distributed object detection.
J. Real-Time Image Processing, 2007

Power-aware computing systems.
IJES, 2007

Exploring temperature-aware design in low-power MPSoCs.
IJES, 2007

Electronic Detection of DNA Hybridization: Toward CMOS Microarrays.
IEEE Design & Test of Computers, 2007

MOCA: A Low-Power, Low-Cost Motion Capture System Based on Integrated Accelerometers.
Adv. in MM, 2007

Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

NoC Design and Implementation in 65nm Technology.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Reducing Interconnect Cost in NoC through Serialized Asynchronous Links.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Introducing tangerine: a tangible interactive natural environment.
Proceedings of the 15th International Conference on Multimedia 2007, 2007

Timing-driven row-based power gating.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

System-Level Design for Nano-Electronics.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A lightweight parallel java execution environment for embedded multiprocessor systems-on-chip.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Multi-processor operating system emulation framework with thermal feedback for systems-on-chip.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

MP-Queue: an Efficient Communication Library for Embedded Streaming Multimedia Platforms.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

Communication-aware stochastic allocation and scheduling framework for conditional task graphs in multi-processor systems-on-chip.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007

Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Dynamic reconfiguration in sensor networks with regenerative energy sources.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Adaptive power management in energy harvesting systems.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Interactive presentation: Improving the fault tolerance of nanometric PLA designs.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

07041 Abstracts Collection - Power-aware Computing Systems.
Proceedings of the Power-aware Computing Systems, 21.01. - 26.01.2007, 2007

07041 Summary - Power-aware Computing Systems.
Proceedings of the Power-aware Computing Systems, 21.01. - 26.01.2007, 2007

Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms.
Proceedings of the 2007 International Conference on Compilers, 2007

Enhancing the spatial resolution of presence detection in a PIR based wireless surveillance network.
Proceedings of the Fourth IEEE International Conference on Advanced Video and Signal Based Surveillance, 2007

Distributed video surveillance using hardware-friendly sparse large margin classifiers.
Proceedings of the Fourth IEEE International Conference on Advanced Video and Signal Based Surveillance, 2007

Exploration of Low Power Adders for a SIMD Data Path.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Linux-Based Data Acquisition and Processing on Palmtop Computer.
IEEE Trans. Instrumentation and Measurement, 2006

Cache coherence tradeoffs in shared-memory MPSoCs.
ACM Trans. Embedded Comput. Syst., 2006

A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Reducing Conflict Misses by Application-Specific Reconfigurable Indexing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

TOM: a web-based integrated approach for identification of candidate disease genes.
Nucleic Acids Research, 2006

Wireless sensor networks: Enabling technology for ambient intelligence.
Microelectronics Journal, 2006

Energy-Efficient Value Based Selective Refresh for Embedded DRAMS.
J. Low Power Electronics, 2006

Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems.
Integration, 2006

Optimized Technique for Dna Structural Properties Discovering.
International Journal on Artificial Intelligence Tools, 2006

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Designing Routing and Message-Dependent Deadlock Free Networks on Chips.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations .
Proceedings of the Embedded Computer Systems: Architectures, 2006

Gesture Signature for Ambient Intelligence Applications: A Feasibility Study.
Proceedings of the Pervasive Computing, 2006

Bio-feedback System for Rehabilitation Based on a Wireless Body Area Network.
Proceedings of the 4th IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2006 Workshops), 2006

Synchronization-driven dynamic speed scaling for MPSoCs.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Dynamic thermal clock skew compensation using tunable delay buffers.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Mining Gene Sets for Measuring Similarities.
Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC 2006), 2006

A Wireless Body Area Sensor Network for Posture Detection.
Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC 2006), 2006

Lazy Scheduling for Energy Harvesting Sensor Nodes.
Proceedings of the From Model-Driven Design to Resource Management for Distributed Embedded Systems, 2006

Reliability Support for On-Chip Memories Using Networks-on-Chip.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Designing application-specific networks on chips with floorplan information.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

STV-Cache: a leakage energy-efficient architecture for data caches.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Real-Time Scheduling with Regenerative Energy.
Proceedings of the 18th Euromicro Conference on Real-Time Systems, 2006

3dID: a low-power, low-cost hand motion capture device.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Exploring "temperature-aware" design in low-power MPSoCs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Combining simulation and formal methods for system-level performance analysis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Application specific NoC design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Enabling fine-grain leakage management by voltage anchor insertion.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Contrasting a NoC and a traditional interconnect fabric with layout awareness.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

An integrated open framework for heterogeneous MPSoC design space exploration.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip.
Proceedings of the 43rd Design Automation Conference, 2006

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration.
Proceedings of the 43rd Design Automation Conference, 2006

A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip.
Proceedings of the 43rd Design Automation Conference, 2006

Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs.
Proceedings of the Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, 2006

MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis.
Proceedings of the Third Conference on Computing Frontiers, 2006

Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images.
Proceedings of the 19th IEEE International Symposium on Computer-Based Medical Systems (CBMS 2006), 2006

2005
State-of-the-Art SoC Communication Architectures.
Proceedings of the Embedded Systems Handbook., 2005

Network-on-Chip Design for Gigascale Systems-on-Chip.
Proceedings of the Embedded Systems Handbook., 2005

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC.
VLSI Signal Processing, 2005

NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.
IEEE Trans. Parallel Distrib. Syst., 2005

Automated DNA fragments recognition and sizing through AFM image processing.
IEEE Trans. Information Technology in Biomedicine, 2005

Discovering Coherent Biclusters from Gene Expression Data Using Zero-Suppressed Binary Decision Diagrams.
IEEE/ACM Trans. Comput. Biology Bioinform., 2005

Error control schemes for on-chip communication links: the energy-reliability tradeoff.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A scalable algorithm for RTL insertion of gated clocks based on ODCs computation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

An efficient profile-based algorithm for scratchpad memory partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Automatic intrinsic DNA curvature computation from AFM images.
IEEE Trans. Biomed. Engineering, 2005

Improving Java performance using dynamic method migration on FPGAs.
IJES, 2005

Pervasive Computing for Interactive Virtual Heritage.
IEEE MultiMedia, 2005

Measuring Efficiency and Executability of Allocation and Scheduling in Multi-Processor Systems-on-Chip.
Intelligenza Artificiale, 2005

Analysis of Error Recovery Schemes for Networks on Chips.
IEEE Design & Test of Computers, 2005

Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Traffic Injection Methodology with Support for System-Level Synchronization.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Simultaneous memory and bus partitioning for SoC architectures.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Fault tolerance overhead in network-on-chip flow control schemes.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Energy efficient NoC design.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Advanced power management of SoC platforms.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs.
Proceedings of the Integrated Circuit and System Design, 2005

Networks on Chips: A Synthesis Perspective.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

A novel approach for network on chip emulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Allocation and Scheduling for MPSoCs via decomposition and no-good generation.
Proceedings of the IJCAI-05, Proceedings of the Nineteenth International Joint Conference on Artificial Intelligence, Edinburgh, Scotland, UK, July 30, 2005

Design and Implementation of WiMoCA Node for a Body Area Wireless Sensor Network.
Proceedings of the Systems Communications 2005 (ICW / ICHSN / ICMCS / SENET 2005), 2005

Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Low-overhead state-retaining elements for low-leakage MTCMOS design.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization Detection.
Proceedings of the 2005 Design, 2005

05141 Abstracts Collection - Power-aware Computing Systems.
Proceedings of the Power-aware Computing Systems, 3.-8. April 2005, 2005

05141 Summary - Power-aware Computing Systems.
Proceedings of the Power-aware Computing Systems, 3.-8. April 2005, 2005

Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation.
Proceedings of the Principles and Practice of Constraint Programming, 2005

Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Network On-Chip Design for Gigascale Systems-on-Chip.
Proceedings of the Industrial Information Technology Handbook, 2005

2004
Adaptive Algorithmic Power Optimization for Multimedia Workload in Mobile Environments.
Proceedings of the Mobile Computing Handbook., 2004

Memory energy minimization by data compression: algorithms, architectures and implementation.
IEEE Trans. VLSI Syst., 2004

A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems.
IEEE Trans. Computers, 2004

Specification and analysis of power-managed systems.
Proceedings of the IEEE, 2004

Packetization and routing analysis of on-chip multiprocessor networks.
Journal of Systems Architecture, 2004

Guest Editorial.
Integration, 2004

Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications.
IEEE Design & Test of Computers, 2004

Post-layout leakage power minimization based on distributed sleep transistor insertion.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Improving Java Performance Using Dynamic Method Migration on FPGAs.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Reducing cache misses by application-specific re-configurable indexing.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Cycle-accurate power analysis for multiprocessor systems-on-a-chip.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design.
Proceedings of the 2004 Design, 2004

Analyzing On-Chip Communication in a MPSoC Environment.
Proceedings of the 2004 Design, 2004

×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip.
Proceedings of the 2004 Design, 2004

Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning.
Proceedings of the 2004 Design, 2004

Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating.
Proceedings of the 2004 Design, 2004

A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks.
Proceedings of the 2004 Design, 2004

An integrated hardware/software approach for run-time scratchpad management.
Proceedings of the 41th Design Automation Conference, 2004

A post-compiler approach to scratchpad mapping of code.
Proceedings of the 2004 International Conference on Compilers, 2004

Enhanced pClustering and Its Applications to Gene Expression Data.
Proceedings of the 4th IEEE International Symposium on BioInformatics and BioEngineering (BIBE 2004), 2004

Techniques for Enhancing Computation of DNA Curvature Molecules.
Proceedings of the 4th IEEE International Symposium on BioInformatics and BioEngineering (BIBE 2004), 2004

2003
Guest editorial.
IEEE Trans. VLSI Syst., 2003

Scheduling battery usage in mobile systems.
IEEE Trans. VLSI Syst., 2003

Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques.
ACM Trans. Embedded Comput. Syst., 2003

Discharge Current Steering for Battery Lifetime Optimization.
IEEE Trans. Computers, 2003

Performance Analysis of Arbitration Policies for SoC Communication Architectures.
Design Autom. for Emb. Sys., 2003

SystemC Cosimulation and Emulation of Multiprocessor SoC Designs.
IEEE Computer, 2003

Statistical Power Estimation of Behavioral Descriptions.
Proceedings of the Integrated Circuit and System Design, 2003

Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Energy-efficient data scrambling on memory-processor interfaces.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A novel architecture for power maskable arithmetic units.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Packetized On-Chip Interconnect Communication Analysis for MPSoC.
Proceedings of the 2003 Design, 2003

SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.
Proceedings of the 2003 Design, 2003

Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems.
Proceedings of the 2003 Design, 2003

Scaling into Ambient Intelligence.
Proceedings of the 2003 Design, 2003

Clock-tree power optimization based on RTL clock-gating.
Proceedings of the 40th Design Automation Conference, 2003

Energy-aware design techniques for differential power analysis protection.
Proceedings of the 40th Design Automation Conference, 2003

Polynomial-time algorithm for on-chip scratchpad memory partitioning.
Proceedings of the International Conference on Compilers, 2003

Advanced power management techniques: going beyond intelligent shutdown.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Power-aware operating systems for interactive systems.
IEEE Trans. VLSI Syst., 2002

Minimizing memory access energy in embedded systems by selective instruction compression.
IEEE Trans. VLSI Syst., 2002

Layout-driven memory synthesis for embedded systems-on-chip.
IEEE Trans. VLSI Syst., 2002

Dynamic frequency scaling with buffer insertion for mixed workloads.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Value-sensitive automatic code specialization for embedded software.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Dynamic Power Management for Nonstationary Service Requests.
IEEE Trans. Computers, 2002

Virtual Simulation of Distributed IP-Based Designs.
IEEE Design & Test of Computers, 2002

A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems.
Design Autom. for Emb. Sys., 2002

Networks on Chips: A New SoC Paradigm.
IEEE Computer, 2002

Power aware network interface management for streaming multimedia.
Proceedings of the 2002 IEEE Wireless Communications and Networking Conference Record, 2002

Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Contents provider-assisted dynamic voltage scaling for low energy multimedia applications.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Parametric timing and power macromodels for high level simulation of low-swing interconnects.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Discharge current steering for battery lifetime optimization.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

An adaptive data compression scheme for memory traffic minimization in processor-based systems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Automated DNA sizing in atomic force microscope images.
Proceedings of the 2002 IEEE International Symposium on Biomedical Imaging, 2002

Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Networks on Chip: A New Paradigm for Systems on Chip Design.
Proceedings of the 2002 Design, 2002

Low Power Error Resilient Encoding for On-Chip Data Buses.
Proceedings of the 2002 Design, 2002

Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors.
Proceedings of the 2002 Design, 2002

Analysis of power consumption on switch fabrics in network routers.
Proceedings of the 39th Design Automation Conference, 2002

Low Power Control Techniques For TFT LCD Displays.
Proceedings of the International Conference on Compilers, 2002

System lifetime extension by battery management: an experimental work.
Proceedings of the International Conference on Compilers, 2002

Memory design techniques for low energy embedded systems.
Kluwer, ISBN: 978-0-7923-7690-3, 2002

2001
Energy-efficient design of battery-powered embedded systems.
IEEE Trans. VLSI Syst., 2001

Discrete-time battery models for system-level low-power design.
IEEE Trans. VLSI Syst., 2001

Event-driven power management.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Synthesis of power-managed sequential components based oncomputational kernel extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Software-controlled processor speed setting for low-power streamingmultimedia.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Energy characterization of embedded real-time operating systems.
SIGARCH Computer Architecture News, 2001

Battery-Driven Dynamic Power Management.
IEEE Design & Test of Computers, 2001

Source code transformation based on software cost analysis.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Powering Networks on Chips: Energy-Efficient and Reliable Interconnect Design for SoCs.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Automatic source code specialization for energy reduction.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Cached-code compression for energy minimization in embedded processors.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Component selection and matching for IP-based design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

On-the-fly layout generation for PTL macrocells.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Extending lifetime of portable systems by battery scheduling.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

An adaptive algorithm for low-power streaming multimedia processing.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Dynamic Voltage Scaling and Power Management for Portable Systems.
Proceedings of the 38th Design Automation Conference, 2001

Statistical Design Space Exploration for Application-Specific Unit Synthesis.
Proceedings of the 38th Design Automation Conference, 2001

From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip.
Proceedings of the 38th Design Automation Conference, 2001

Processor frequency setting for energy minimization of streaming multimedia application.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Glitch power minimization by selective gate freezing.
IEEE Trans. VLSI Syst., 2000

A survey of design techniques for system-level dynamic power management.
IEEE Trans. VLSI Syst., 2000

Regression-based RTL power modeling.
ACM Trans. Design Autom. Electr. Syst., 2000

Synthesis of low-power selectively-clocked systems from high-level specification.
ACM Trans. Design Autom. Electr. Syst., 2000

System-level power optimization: techniques and tools.
ACM Trans. Design Autom. Electr. Syst., 2000

Architectures and synthesis algorithms for power-efficient businterfaces.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

A multilevel engine for fast power simulation of realistic inputstreams.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation.
IEEE Design & Test of Computers, 2000

Dynamic power management for portable systems.
Proceedings of the MOBICOM 2000, 2000

Source Code Optimization and Profiling of Energy Consumption in Embedded Systems.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Requester-Aware Power Reduction.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Battery-Driven Dynamic Power Management of Portable Systems.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Operating-system directed power reduction.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

A recursive algorithm for low-power memory partitioning.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Supporting system-level power exploration for DSP applications.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Regression-based RTL power models for controllers.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Dynamic Power Management of Laptop Hard Disk.
Proceedings of the 2000 Design, 2000

Quantitative Comparison of Power Management Algorithms.
Proceedings of the 2000 Design, 2000

Virtual Fault Simulation of Distributed IP-Based Designs.
Proceedings of the 2000 Design, 2000

A Discrete-Time Battery Model for High-Level Power Estimation.
Proceedings of the 2000 Design, 2000

Hardware/software IP protection.
Proceedings of the 37th Conference on Design Automation, 2000

Synthesis of application-specific memories for power optimization in embedded systems.
Proceedings of the 37th Conference on Design Automation, 2000

Low-power task scheduling for multiple devices.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers.
ACM Trans. Design Autom. Electr. Syst., 1999

Policy optimization for dynamic power management.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting.
IEEE Trans. Computers, 1999

Event-Driven Power Management of Portable Systems.
Proceedings of the 12th International Symposium on System Synthesis, 1999

Energy-efficient design of battery-powered embedded systems.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Efficient switching activity computation during high-level synthesis of control-dominated designs.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Selective instruction compression for memory energy reduction in embedded systems.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

System-level power optimization: techniques and tools.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Dynamic power management using adaptive learning tree.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Specification and Validation of Distributed IP-Based Designs with JavaCAD.
Proceedings of the 1999 Design, 1999

Dynamic Power Management for non-stationary service requests.
Proceedings of the 1999 Design, 1999

Glitch Power Minimization by Gate Freezing.
Proceedings of the 1999 Design, 1999

Cycle-Accurate Simulation of Energy Consumption in Embedded Systems.
Proceedings of the 36th Conference on Design Automation, 1999

Virtual Simulation of Distributed IP-based Designs.
Proceedings of the 36th Conference on Design Automation, 1999

Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses.
Proceedings of the 36th Conference on Design Automation, 1999

Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Robust RTL power macromodels.
IEEE Trans. VLSI Syst., 1998

Power optimization of core-based systems by address bus encoding.
IEEE Trans. VLSI Syst., 1998

Iterative remapping for logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Telescopic units: a new paradigm for performance optimization of VLSI designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Regression Models for Behavioral Power Estimation.
Integrated Computer-Aided Engineering, 1998

System-level power estimation and optimization.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Monitoring system activity for OS-directed dynamic power management.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Node sampling: a robust RTL power modeling approach.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Dynamic power management of electronic systems.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Timed Supersetting and the Synthesis of Telescopic Units.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Characterization-Free Behavioral Power Modeling.
Proceedings of the 1998 Design, 1998

Address Bus Encoding Techniques for System-Level Power Optimization.
Proceedings of the 1998 Design, 1998

Policy Optimization for Dynamic Power Management.
Proceedings of the 35th Conference on Design Automation, 1998

In-Place Power Optimization for LUT-Based FPGAs.
Proceedings of the 35th Conference on Design Automation, 1998

Computational Kernels and their Application to Sequential Power Optimization.
Proceedings of the 35th Conference on Design Automation, 1998

Dynamic power management - design techniques and CAD tools.
Kluwer, ISBN: 978-0-7923-8086-3, 1998

1997
Clock Skew Optimization for Peak Current Reduction.
VLSI Signal Processing, 1997

Gate-level power and current simulation of CMOS integrated circuits.
IEEE Trans. VLSI Syst., 1997

A survey of Boolean matching techniques for library binding.
ACM Trans. Design Autom. Electr. Syst., 1997

Re-mapping for low power under tight timing constraints.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

System-level power optimization of special purpose applications: the beach solution.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Generalized matching from theory to application.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Fast power estimation for deterministic input streams.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Adaptive least mean square behavioral power modeling.
Proceedings of the European Design and Test Conference, 1997

Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks.
Proceedings of the European Design and Test Conference, 1997

Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Automatic synthesis of low-power gated-clock finite-state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Clock skew optimization for peak current reduction.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Gate-level current waveform simulation of CMOS integrated circuits.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Distributed EDA Tool Integration: The PPP Paradigm.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Design for Testability of Gated-Clock FSMs.
Proceedings of the 1996 European Design and Test Conference, 1996

Power Estimation of Cell-Based CMOS Circuits.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Analysis of glitch power dissipation in CMOS ICs.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Transformation and synthesis of FSMs for low-power gated-clock implementation.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1994
Saving Power by Synthesizing Gated Clocks for Sequential Circuits.
IEEE Design & Test of Computers, 1994


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