Tero Partanen

Orcid: 0000-0002-9975-0535

According to our database1, Tero Partanen authored at least 9 papers between 2006 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2025
Energy-Efficient Saliency-Guided Video Coding Framework for Real-Time Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2025

2024
Luma Range Scaling for Enhanced VVC Efficiency in Video Coding for Machines.
Proceedings of the 26th IEEE International Workshop on Multimedia Signal Processing, 2024

Feasibility Study of Multi-Layer VVC Coding Scheme for Hybrid Machine-Human Consumption.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2024

Motion-Vector-Driven Lightweight ROI Tracking for Real-Time Saliency-Guided Video Encoding.
Proceedings of the 32nd European Signal Processing Conference, 2024

2021
High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Implementation and Accuracy Evaluation of Fixed Camera-Based Object Positioning System Employing CNN-Detector.
Proceedings of the 9th European Workshop on Visual Information Processing, 2021

2008
Low-power signal acquisition for galileo satellite navigation system.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Low-Power Twiddle Factor Unit for FFT Computation.
Proceedings of the Embedded Computer Systems: Architectures, 2007

2006
Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform.
Proceedings of the Embedded Computer Systems: Architectures, 2006


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