Thomas Steininger

According to our database, Thomas Steininger authored at least 12 papers between 2004 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2010

Model reduction techniques for the formal verification of hardware dependent software.

Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

TLM+ modeling of embedded HW/SW systems.

Wolfgang Ecker, Volkan Esen, Robert Schwencker, Thomas Steininger, Michael Velten

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Automated assertion transformation across multiple abstraction levels.

Thomas Steininger

PhD thesis, 2009

2007

Requirements and Concepts for Transaction Level Assertion Refinement.

Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten

Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Interactive presentation: Implementation of a transaction level assertion framework in SystemC.

Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance.

Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Requirements and Concepts for Transaction Level Assertions.

Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Specification Language for Transaction Level Assertions.

Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

IP Library For Temporal SystemC Assertions.

Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Jacob Smit

Proceedings of the Forum on specification and Design Languages, 2006

Case Study on Transaction Level Modeling.

Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten

Proceedings of the Forum on specification and Design Languages, 2006

2004

Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach.

Jens Bieger, Sorin A. Huss, Michael Jung, Stephan Klaus, Thomas Steininger

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking.

Wolfgang Ecker, Volkan Esen, Thomas Steininger, Martin Zambaldi

Proceedings of the 7th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2004), 2004