Tomoaki Ukezono

Proceedings of the IEEE Region 10 Conference, 2023

Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition.

[BibT_eX]

[DOI]

Hiroyuki Hama

Proceedings of the 20th International SoC Design Conference, 2023

Investigation for Impact of Environmental Noise on Power Analysis Attacks.

[BibT_eX]

[DOI]

Ryoma Katsube

Proceedings of the 20th International SoC Design Conference, 2023

Leveraging Approximate Computing for IoT Image Transmission.

[BibT_eX]

[DOI]

Hiroyuki Hama

Proceedings of the 20th International SoC Design Conference, 2023

Negative Impact of Approximated Signed Addition on Power Reduction.

[BibT_eX]

[DOI]

Hiroyuki Hama

Proceedings of the International Symposium on Devices, Circuits and Systems, 2023

Effect of High Frequency Noise Using DCMs in FPGA on Power Analysis Attack.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Communications and Information Technologies, 2023

A Cost-aware Generation Method of Disposable Random Value Exploiting Parallel S-box Implementation for Tamper-resistant AES Design.

[BibT_eX]

[DOI]

Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, 2023

2022

An Extremely Light-Weight Countermeasure to Power Analysis Attack in Dedicated Circuit for AES.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

An Accuracy-Controllable Approximate Adder for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT 2022), 2022

2021

Design of a 32-bit Accuracy-Controllable Approximate Multiplier for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

2020

Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

An Accuracy-Configurable Adder for Low-Power Applications.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2020

A Dynamically Configurable Approximate Array Multiplier with Exact Mode.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Computer and Communication Systems, 2020

2019

Evaluations of CMA with Error Corrector in Image Processing Circuit.

[BibT_eX]

[DOI]

Int. J. Netw. Comput., 2019

Design and Analysis of Approximate Multipliers with a Tree Compressor.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Trading Accuracy for Power with a Configurable Approximate Adder.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2019

Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Pacific Rim International Symposium on Dependable Computing, 2019

On Applications of Configurable Approximation to Irregular Voltage.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Low-Power Approximate Multiply-Add Unit.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Tolerating Aging-Induced Timing Violations Via Configurable Approximations.

[BibT_eX]

[DOI]

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

Correcting Sign Calculation Errors in Configurable Approximations.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018

Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A low-power configurable adder for approximate applications.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Exploiting Configurability for Correct Sign Calculation in an Approximate Adder.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2018

Approximate Adder Generation for Image Processing Using Convolutional Neural Network.

[BibT_eX]

[DOI]

Ryuta Ishida

Proceedings of the International SoC Design Conference, 2018

A Low-Power Yet High-Speed Configurable Adder for Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Error Corrector for Dynamically Accuracy-Configurable Approximate Adder.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

A low-power high-speed accuracy-controllable approximate multiplier design.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2013

Filtering Insertions into a Small Instruction Cache in Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Computing and Networking, 2013

2010

Reduction of leakage energy in low level caches.

[BibT_eX]

[DOI]

Kiyofumi Tanaka

Proceedings of the International Green Computing Conference 2010, 2010

2008

HDOS: An Infrastructure for Dynamic Optimization.

[BibT_eX]

Kiyofumi Tanaka

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2008

Dynamic binary code translation for data prefetch optimization.

[BibT_eX]

[DOI]