Tomoya Ozaki

According to our database, Tomoya Ozaki authored at least 3 papers between 2015 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface.

Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

IEICE Trans. Inf. Syst., 2016

2015

Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips.

Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Augmenting low-latency HPC network with free-space optical links.

Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015