Toshio Sudo

According to our database, Toshio Sudo authored at least 6 papers between 1995 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Anti-resonance peak frequency control by variable on-die capacitance.

Wataru Ichimura, Sho Kiyoshige, Masahiro Terasaki, Ryota Kobayashi, Genki Kubo, Hiroki Otsuka, Toshio Sudo

Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures.

Haruya Fujita, Hiroki Takatani, Yosuke Tanaka, Shohei Kawaguchi, Masaomi Sato, Toshio Sudo

Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

2011

PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure.

Yoshiaki Oizono, Yoshitaka Nabeshima, Takafumi Okumura, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2009

Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substrates.

Katsuya Kikuchi, Koichi Takemura, Chihiro Ueda, Osamu Shimada, Toshio Gomyo, Yukiharu Takeuchi, Toshikazu Okubo, Kazuhiro Baba, Masahiro Aoyagi, Toshio Sudo, Kanji Otsuka

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2005

Radiated Harmonics Characterization of CMOS Test Chip with On-Chip Decoupling Capacitance.

Toshio Sudo

IEICE Trans. Commun., 2005

1995

Present and future directions for multichip module technologies.

Toshio Sudo

IEEE J. Solid State Circuits, April, 1995