Toyohito Ikeya

According to our database, Toyohito Ikeya authored at least 4 papers between 2000 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor.

Kazuo Otsuga, Masafumi Onouchi, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa

Proceedings of the IEEE 25th International SOC Conference, 2012

2011

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process.

Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2001

A Practical Logic BIST for ASIC Designs.

Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Toyohito Ikeya, Masatoshi Kawashima

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

A BIST approach for very deep sub-micron (VDSM) defects.

Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000