Kazumasa Yanagisawa

According to our database1, Kazumasa Yanagisawa authored at least 10 papers between 2004 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2014

40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2012
An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor.
Proceedings of the IEEE 25th International SOC Conference, 2012

2011
A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues.
IEEE J. Solid State Circuits, 2011

A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2007
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.
IEEE J. Solid State Circuits, 2007

2006
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


2004
Probabilistic crosstalk delay estimation for ASICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004


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