Kazumasa Yanagisawa

According to our database, Kazumasa Yanagisawa authored at least 16 papers between 1997 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique.

Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa

IEEE Trans. Very Large Scale Integr. Syst., 2014

40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU.

Yoshisato Yokoyama, Yuichiro Ishii, Hidemitsu Kojima, Atsushi Miyanishi, Yoshiki Tsujihashi, Shinobu Asayama, Kazutoshi Shiba, Koji Tanaka, Tatsuya Fukuda, Koji Nii, Kazumasa Yanagisawa

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2012

An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor.

Kazuo Otsuga, Masafumi Onouchi, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa

Proceedings of the IEEE 25th International SOC Conference, 2012

2011

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues.

Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, Kazumasa Yanagisawa

IEEE J. Solid State Circuits, 2011

A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias.

Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Kazuyoshi Okamoto, Kazutaka Mori, Kazumasa Yanagisawa

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process.

Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2007

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.

Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie

IEEE J. Solid State Circuits, 2007

2006

90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique.

Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara

IEEE J. Solid State Circuits, 2006

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor.

Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Hierarchical power distribution and power management scheme for a single chip mobile processor.

Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno

Proceedings of the 43rd Design Automation Conference, 2006

2005

A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor.

Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada

IEEE J. Solid State Circuits, 2005

2004

Probabilistic crosstalk delay estimation for ASICs.

Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato, Kazuko Sakamoto, Saburo Hojo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2002

A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit.

Masanao Yamaoka, Kazumasa Yanagisawa, Shoji Shukuri, Katsuhiro Norisue, Koichiro Ishibashi

IEEE J. Solid State Circuits, 2002

2001

CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip.

Shoji Shukuri, Kazumasa Yanagisawa, Koichiro Ishibashi

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

An efficient method of applying hot-carrier reliability simulation to logic design.

Hisuko Sato, Mariko Ohtsuka, Kazumasa Yanagisawa, Peter M. Lee

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1997

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip.

Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome

IEEE J. Solid State Circuits, 1997