Trevor C. Caldwell

According to our database1, Trevor C. Caldwell authored at least 16 papers between 2005 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Some Extensions of the Crouzeix-Palencia Result.
SIAM J. Matrix Anal. Appl., 2018

2017
High-speed oversampled continuous-time analog-to-digital converters.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Near Normal Dilations of Nonnormal Matrices and Linear Operators.
SIAM J. Matrix Anal. Appl., 2016

A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016

15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
A Reconfigurable ΔΣ ADC With Up to 100 MHz Bandwidth Using Flash Reference Shuffling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Advances in high-speed continuous-time delta-sigma modulators.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A reconfigurable ΔΣ modulator with up to 100 MHz bandwidth using flash reference shuffling.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f<sub>0</sub> = 450 MHz Using 550 mW.
IEEE J. Solid State Circuits, 2012

A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2010
Incremental Data Converters at Low Oversampling Ratios.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
An 8th-order MASH delta-sigma with an OSR of 3.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2006
A time-interleaved continuous-time ΔΣ modulator with 20-MHz signal bandwidth.
IEEE J. Solid State Circuits, 2006

2005
A time-interleaved continuous-time ΔΣ modulator with 20MHz signal bandwidth.
Proceedings of the 31st European Solid-State Circuits Conference, 2005


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