Jeffrey C. Gealow

According to our database1, Jeffrey C. Gealow authored at least 12 papers between 1996 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2018
A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017
A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology.
IEEE J. Solid State Circuits, 2017

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016

Foreword.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2015

2014
Introduction to the Special Issue on the 2013 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2014

2004
GSM DAC with new segmented mismatch shaping technique.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

1998
Invited Address: Integrated Memory/Logic Architecture for Image Processing.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1996
System design for pixel-parallel image processing.
IEEE Trans. Very Large Scale Integr. Syst., 1996


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