Truong Nguyen

Orcid: 0000-0002-7422-4600

Affiliations:
  • Ho Chi Minh City University of Technology (HCMUT), Department of Electronics Engineering, Faculty of Electrical and Electronics Engineering, Vietnam
  • Vietnam National University, Ho Chi Minh City, Vietnam
  • CEA-LETI, MINATEC Campus, Grenoble, France
  • University of Cergy-Pontoise, ETIS, France (PhD 2017)
  • Vietnam National University, HoChiMinh City, Vietnam


According to our database1, Truong Nguyen authored at least 15 papers between 2013 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
A Deep-Learning Framework for Land-Sliding Classification from Remote Sensing Image.
CoRR, July, 2025

SEMT: Static-Expansion-Mesh Transformer Network Architecture for Remote Sensing Image Captioning.
CoRR, July, 2025

RMAU-NET: A Residual-Multihead-Attention U-Net Architecture for Landslide Segmentation and Detection from Remote Sensing Images.
CoRR, July, 2025

2024
Deepfake Audio Detection Using Spectrogram-based Feature and Ensemble of Deep Learning Models.
Proceedings of the 2024 IEEE 5th International Symposium on the Internet of Sounds (IS2), Erlangen, Germany, September 30, 2024

2023
A Robust and Low Complexity Deep Learning Model for Remote Sensing Image Classification.
Proceedings of the 2023 8th International Conference on Intelligent Information Technology, 2023

2022
High-Performance and Low-Complexity Decoding Algorithms for 5G Low-Density Parity-Check Codes.
J. Commun., 2022

2020
Deep Learning Framework Applied for Predicting Anomaly of Respiratory Sounds.
CoRR, 2020

2018
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2017
Efficient Hardware Implementations of LDPC Decoders, through Exploiting Impreciseness in Message-Passing Decoding Algorithms. (Mise en oeuvre matérielle de décodeurs LDPC haut débit, en exploitant la robustesse du décodage par passage de messages aux imprécisions de calcul).
PhD thesis, 2017

High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders.
Proceedings of the 2017 IEEE International Conference on Communications Workshops, 2017

2016
Non-surjective finite alphabet iterative decoders.
Proceedings of the 2016 IEEE International Conference on Communications, 2016

Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Code-aware quantizer design for finite-precision min-sum decoders.
Proceedings of the 2016 IEEE International Black Sea Conference on Communications and Networking, 2016

2015
FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2013
Design and Implementation of a SoPC System for Speech Recognition.
Proceedings of the Multimedia and Ubiquitous Engineering, 2013


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