Sorin Cotofana

J. Parallel Distributed Comput., 2014

Critical transistors nexus based circuit-level aging assessment and prediction.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

Efficient Method for Designing Modulo {2n ± k} Multipliers.

[BibT_eX]

[DOI]

Héctor Pettenghi

Leonel Sousa

J. Circuits Syst. Comput., 2014

Transmission Channel Noise Aware Energy Effective LDPC Decoding.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

Towards energy effective LDPC decoding by exploiting channel noise variability.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Robust sub-powered asynchronous logic.

[BibT_eX]

[DOI]

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Energy effective 3D stacked hybrid NEMFET-CMOS caches.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014

Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

An efficient residue-to-binary converter for the new moduli set {2n/2 ± 1, 22n+1, 2n + 1}.

[BibT_eX]

[DOI]

Hillary Siewobr

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013

A nonlinear degradation path dependent end-of-life estimation framework from noisy observations.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2013

A direct measurement scheme of amalgamated aging effects with novel on-chip sensor.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A low cost method to tolerate soft errors in the NoC router control plane.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Ultra low power NEMFET based logic.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Lifetime reliability assessment with aging information from low-level sensors.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Is TSV-based 3D integration suitable for inter-die memory repair?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

3D stacked wide-operand adders: A case study.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

An effective New CRT based reverse converter for a novel moduli set {22n+1 - 1, 22n+1, 22n - 1}.

[BibT_eX]

[DOI]

Edem Kwedzo Bankas

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012

Variation tolerant on-chip degradation sensors for dynamic reliability management systems.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

Context aware slope based transistor-level aging model.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms.

[BibT_eX]

[DOI]

Ashkan Beyranvand Nejad

Ba Thang Nguyen

Kees Goossens

Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012

A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip.

[BibT_eX]

[DOI]

Ye Lu

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Stigmergic search with single electron tunneling technology based memory enhanced hubs.

[BibT_eX]

[DOI]

Saleh Safiruddin

Ferdinand Peper

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

A Markovian, variation-aware circuit-level aging model.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Is the road towards "Zero-Energy" paved with NEMFET-based power management?

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 3D stacked high performance scalable architecture for 3D Fourier Transform.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints.

[BibT_eX]

[DOI]

Andrew Nelson

Anca Molnos

Ashkan Beyranvand Nejad

Davit Mirzoyan

Kees Goossens

Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education, 2012

2011

An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set 2n+1, 2n, 2n-1.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Functional unit sharing between stacked processors in 3D integrated systems.

[BibT_eX]

[DOI]

Demid Borodin

Winston Siauw

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Towards "zero-energy" using NEMFET-based power management for 3D hybrid stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Analysis of delay mismatching of digital circuits caused by common environmental fluctuations.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Composable local memory organisation for streaming applications on embedded MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 8th Conference on Computing Frontiers, 2011

2010

An improved RNS reverse converter for the {22n+1-1, 2n, 2n-1} moduli set.

[BibT_eX]

[DOI]

Ricardo Chaves

Leonel Sousa

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A unified addition structure for moduli set {2n-1, 2n, 2n+1} based on a novel RNS representation.

[BibT_eX]

[DOI]

Somayeh Timarchi

Mahmood Fazlali

Proceedings of the 28th International Conference on Computer Design, 2010

Memoryless RNS-to-binary converters for the {2n+1 - 1, 2n, 2n - 1} moduli set.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009

Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Emerging non-CMOS nanoelectronic devices - What are they?.

[BibT_eX]

[DOI]

Nor Zaidi Haron

Said Hamdioui

Proceedings of the 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2009

Can SG-FET Replace FET in Sleep Mode Circuits?

[BibT_eX]

[DOI]

Arjan J. van Genderen

Dimitrios Tsamados

Adrian M. Ionescu

Proceedings of the Nano-Net - 4th International ICST Conference, 2009

Adaptive Clock Scheduling for pipelined structures.

[BibT_eX]

[DOI]

Ben Kuiper

Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

An O(n) Residue Number System to Mixed Radix Conversion Technique.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A reverse converter for the new 4-moduli set {2n + 3, 2n + 2, 2n + 1, 2n}.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

GRAAL: A Framework for Low-Power 3D Graphics Accelerators.

[BibT_eX]

[DOI]

IEEE Computer Graphics and Applications, 2008

Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits.

[BibT_eX]

[DOI]

Saleh Safiruddin

Ferdinand Peper

Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Bitstream compression techniques for Virtex 4 FPGAs.

[BibT_eX]

[DOI]

Radu Andrei Stefan

Proceedings of the FPL 2008, 2008

Compositional, dynamic cache management for embedded chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Generalized matrix method for efficient residue to decimal conversion.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A residue to binary converter for the {2n + 2, 2n + 1, 2n} moduli set.

[BibT_eX]

[DOI]

Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2007

Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2007

2006

Throughput optimization via cache partitioning for embedded multiprocessors.

[BibT_eX]

[DOI]

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology.

[BibT_eX]

[DOI]

Cor Meenderinck

Proceedings of the Embedded Computer Systems: Architectures, 2006

Electron counting based high-radix multiplication in single electron tunneling technology.

[BibT_eX]

[DOI]

Cor Meenderinck

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Consciousness for modeling intelligence - simulating the evolution by closure to the inverse.

[BibT_eX]

Tudor Niculiu

Cristian Lupu

Proceedings of the ICINCO 2006, 2006

Compositional, efficient caches for a chip multi-processor.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

IEEE-Compliant IDCT on FPGA-Augmented TriMedia.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2005

Addition Related Arithmetic Operations via Controlled Transport of Charge.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Compositional Memory Systems for Multimedia Communicating Tasks.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology.

[BibT_eX]

[DOI]

Cor Meenderinck

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

CONAN - A Design Exploration Framework for Reliable Nano-Electronics.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

Pel reconstruction on FPGA-augmented TriMedia.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Analog-to-digital converter based on single-electron tunneling transistors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Single-electron tunneling transistor implementation of periodic symmetric functions.

[BibT_eX]

[DOI]

Chaohong Hu

Jianfei Jiang

IEEE Trans. Circuits Syst. II Express Briefs, 2004

High-Level Energy Estimation for ARM-Based SOCs.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic.

[BibT_eX]

[DOI]

Peter Celinski

Derek Abbott

Proceedings of the Integrated Circuit and System Design, 2004

Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Low cost and latency embedded 3D graphics reciprocation.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Analysis of analog to digital converter based on single-electron tunnelling transistors.

[BibT_eX]

Chaohong Hu

Jianfei Jiang

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Compositional Memory Systems for Data Intensive Applications.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

GRAAL - A Development Framework for Embedded Graphics Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Efficient Hardware for Antialiasing Coverage Mask Generation.

[BibT_eX]

[DOI]

Proceedings of the 2004 Computer Graphics International (CGI 2004), 16-19 June 2004, 2004

Binary Multiplication based on Single Electron Tunneling.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003

Microcode Processing: Positioning and Directions.

[BibT_eX]

[DOI]

IEEE Micro, 2003

Evaluation Methodology for Single Electron Encoded Threshold Logic Gates.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SOC: From Systems to Chips, 2003

D-SAB: A Sparse Matrix Benchmark Suite.

[BibT_eX]

[DOI]

Pyrrhos Stathis

Proceedings of the Parallel Computing Technologies, 2003

CMOS Implementation of Generalized Threshold Functions.

[BibT_eX]

[DOI]

Marius Padure

Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003

A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder.

[BibT_eX]

[DOI]

Peter Celinski

Derek Abbott

Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003

Design and experimental results of a CMOS flip-flop featuring embedded threshold logic.

[BibT_eX]

[DOI]

Marius Padure

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Area efficient, high speed parallel counter circuits using charge recycling threshold logic.

[BibT_eX]

[DOI]

Peter Celinski

Derek Abbott

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A Hierarchical Sparse Matrix Storage Format for Vector Processors.

[BibT_eX]

[DOI]

Pyrrhos Stathis

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2002

Microcoded Reconfigurable Embedded Processors: Current Developments.

[BibT_eX]

[DOI]

Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study.

[BibT_eX]

[DOI]

Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

A low-power threshold logic family.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A full adder implementation using SET based linear threshold gates.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Alternatives in FPGA-based SAD implementations.

[BibT_eX]

[DOI]

Bastiaan Stougie

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Field-Programmable Custom Computing Machines - A Taxonomy -.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

A Sum of Absolute Differences Implementation in FPGA Hardware.

[BibT_eX]

[DOI]

Proceedings of the 28th EUROMICRO Conference 2002, 4-6 September 2002, Dortmund, Germany, 2002

Hierarchical Intellignet Mixed Simulation.

[BibT_eX]

Tudor Niculiu

Proceedings of the 16th European Simulation Multiconference: Modelling and Simulation 2002, 2002

2001

Coarse Reconfigurable Multimedia Unit Extension.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

The MOLEN rho-mu-Coded Processor.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2001

An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia.

[BibT_eX]

[DOI]

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

Topic 15+20: Multimedia and Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2001: Parallel Processing, 2001

2000

Signed Digit Addition and Related Operations with Threshold Logic.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

General-Purpose Processor Huffman Encoding Extension.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Information Technology (ITCC 2000), 2000

Multimedia Enhanced General-Purpose Processors.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000

Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note).

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

Counter Based Superscalar Instruction Issuing.

[BibT_eX]

[DOI]

Ben H. H. Juurlink

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Hierarchical interfaces for hardware software systems.

[BibT_eX]

Tudor Niculiu

Chouki Aktouf

Proceedings of the 14th European Simulation Multiconference, 2000

1999

Serial binary multiplication with feed-forward neural networks.

[BibT_eX]

[DOI]

Neurocomputing, 1999

Vector ISA Extension for Sparse Matrix-Vector Multiplication.

[BibT_eX]

[DOI]

Pyrrhos Stathis

Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998

Periodic symmetric functions, serial addition, and multiplication with neural networks.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1998

On the Design Complexity of the Issue Logic of Superscalar Machines.

[BibT_eX]

[DOI]

Proceedings of the 24th EUROMICRO '98 Conference, 1998

1996

delta-Bit serial binary addition with linear threshold networks.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1996

2-1 Additions and Related Arithmetic Operations with Threshold Logic.

[BibT_eX]

[DOI]

Koen Bertels

IEEE Trans. Computers, 1996

Serial Binary Addition with Polynominally Bounded Weights.

[BibT_eX]

[DOI]