Oana Boncalo

According to our database, Oana Boncalo authored at least 51 papers between 2007 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes.

Oana Boncalo, Alexandru Amaricai

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2021

Calibration of CO, NO2, and O3 Using Airify: A Low-Cost Sensor Cluster for Air Quality Monitoring.

Marian-Emanuel Ionascu, Núria Castell, Oana Boncalo, Philipp Schneider, Marius Darie, Marius Marcu

Sensors, 2021

2020

Layered LDPC decoder in-order message access scheduling: a case study.

Oana Boncalo, Alexandru Amaricai

Proceedings of the 14th IEEE International Symposium on Applied Computational Intelligence and Informatics, 2020

2019

Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation.

Oana Boncalo, Gyorgy Kolumban-Antal, Alexandru Amaricai, Valentin Savin, David Declercq

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller.

Oana Boncalo, Alexandru Amaricai, Zsófia Lendek

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018

Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders.

Thien Truong Nguyen-Ly, Valentin Savin, Khoa Le, David Declercq, Fakhreddine Ghaffari, Oana Boncalo

IEEE Trans. Very Large Scale Integr. Syst., 2018

Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.

Khoa Le, David Declercq, Fakhreddine Ghaffari, Lounis Kessal, Oana Boncalo, Valentin Savin

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Code-design for efficient pipelined layered LDPC decoders with bank memory organization.

Oana Boncalo, Gyorgy Kolumban-Antal, David Declercq, Valentin Savin

Microprocess. Microsystems, 2018

An Imprecise Stopping Criterion Based on In-Between Layers Partial Syndromes.

David Declercq, Valentin Savin, Oana Boncalo, Fakhreddine Ghaffari

IEEE Commun. Lett., 2018

Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.

Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin, Oana Boncalo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding.

Oana Boncalo, Alexandru Amaricai, Sergiu Nimara

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017

On the Redundant Representation of Partial Remainders in Radix-4 SRT Dividers.

Alexandru Amaricai, Ovidiu Sicoe, Oana Boncalo

J. Circuits Syst. Comput., 2017

Unrolled layered architectures for non-surjective finite alphabet iterative decoders.

Oana Boncalo, Valentin Savin, Alexandru Amaricai

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders.

Oana Boncalo, Alexandru Amaricai

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016

Variable throughput LDPC decoders using SIMD-based adaptive quantization.

Virgil E. Petcu, Oana Boncalo, Alexandru Amaricai, Valentin Savin

Proceedings of the 39th International Conference on Telecommunications and Signal Processing, 2016

Configurable FPGA architecture for hardware-software merge sorting.

Patricia Carla Petrut, Alexandru Amaricai, Oana Boncalo

Proceedings of the 2016 MIXDES, 2016

Multi Clock Flooded LDPC Decoding Architecture with Reduced Memory and Interconnect.

Oana Boncalo, Ioana Mot

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Reliability analysis of memory centric LDPC decoders under probabilistic storage failures.

Alexandru Amaricai, Sergiu Nimara, Oana Boncalo, Emanuel M. Popovici

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Non-surjective finite alphabet iterative decoders.

Thien Truong Nguyen-Ly, Khoa Le, Valentin Savin, David Declercq, Fakhreddine Ghaffari, Oana Boncalo

Proceedings of the 2016 IEEE International Conference on Communications, 2016

QC-LDPC Gear-Like Decoder Architecture with Multi-domain Quantization.

Oana Boncalo

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization.

Sergiu Nimara, Oana Boncalo, Alexandru Amaricai, Mircea Popa

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting.

Marius Marcu, Oana Boncalo, Madalin Ghenea, Alexandru Amaricai, Jan Weinstock, Rainer Leupers, Zheng Wang, Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, Cosmin Cernazanu-Glavan, Lucian Bara, Marian Ionascu

Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015

Hardware support for performance measurements and energy estimation of OpenRISC processor.

Lucian Bara, Oana Boncalo, Marius Marcu

Proceedings of the 10th IEEE Jubilee International Symposium on Applied Computational Intelligence and Informatics, 2015

FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding.

Truong Nguyen-Ly, Khoa Le, Fakhreddine Ghaffari, Alexandru Amaricai, Oana Boncalo, Valentin Savin, David Declercq

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders.

Andrei Hera, Oana Boncalo, Constantina-Elena Gavriliu, Alexandru Amaricai, Valentin Savin, David Declercq, Fakhreddine Ghaffari

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques.

Ioana Mot, Oana Boncalo, Alexandru Amaricai

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Template-based QC-LDPC decoder architecture generation.

Oana Boncalo, Petru Florin Mihancea, Alexandru Amaricai

Proceedings of the 10th International Conference on Information, 2015

2014

Low-precision DSP-based floating-point multiply-add fused for field programmable gate arrays.

Alexandru Amaricai, Oana Boncalo, Constantina-Elena Gavriliu

IET Comput. Digit. Tech., 2014

Cost effective FPGA probabilistic fault emulation.

Oana Boncalo, Alexandru Amaricai, Christian Spagnol, Emanuel M. Popovici

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Memory efficient implementation of self-corrected min-sum LDPC decoder.

Oana Boncalo, Alexandru Amaricai, Valentin Savin

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing.

Oana Boncalo, Alexandru Amaricai, Andrei Hera, Valentin Savin

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

An FPGA sliding window-based architecture harris corner detector.

Alexandru Amaricai, Constantina-Elena Gavriliu, Oana Boncalo

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits.

Alexandru Amaricai, Sergiu Nimara, Oana Boncalo, Jiaoyan Chen, Emanuel M. Popovici

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013

SRT radix-2 dividers with (5, 4) redundant representation of partial remainder.

Alexandru Amaricai, Oana Boncalo

Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

FPGA implementation of hybrid fixed point - Floating point multiplication.

Alexandru Amaricai, Oana Boncalo, Ovidiu Sicoe, Marius Marcu

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

2012

A cycle-count-accurate simulation platform with enhanced design exploration capability.

Oana Boncalo, Alin Dobre, Alexandru Amaricai, Andrei V. Tanase

Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012

Automatic Generation of FPGA Hardware Accelerators for Graphics Applications.

Alexandru Amaricai, Oana Boncalo

Proceedings of the PECCS 2012, 2012

FPGA implementation of very high radix square root with prescaling.

Alexandru Amaricai, Oana Boncalo

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Models and implementations of hardware interface modules in a multi-processor system-on-chip simulator.

Alexandru Amaricai, Alin Dobre, Oana Boncalo, Andrei V. Tanase, Camelia Valuch

Proceedings of the 6th IEEE International Symposium on Applied Computational Intelligence and Informatics, 2011

2010

Design Issues and Implementations for Floating-Point Divide-Add Fused.

Alexandru Amaricai, Mircea Vladutiu, Oana Boncalo

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Quantum circuit's reliability assessment with VHDL-based simulated fault injection.

Oana Boncalo, Alexandru Amaricai, Mihai Udrescu, Mircea Vladutiu

Microelectron. Reliab., 2010

2009

Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation.

Oana Boncalo, Alexandru Amaricai

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation.

Alexandru Amaricai, Oana Boncalo

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Floating point multiplication rounding schemes for interval arithmetic.

Alexandru Amaricai, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan, Oana Boncalo

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007

Design for dependability in emerging technologies.

Lucian Prodan, Mihai Udrescu, Oana Boncalo, Mircea Vladutiu

ACM J. Emerg. Technol. Comput. Syst., 2007

Simulated Fault Injection for Quantum Circuits Based on Simulator Commands.

Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai

Proceedings of the 4th International Symposium on Applied Computational Intelligence and Informatics, 2007

Assessing quantum circuits reliability with mutant-based simulated fault injection.

Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment.

Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition.

Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor.

Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits.

Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai

Proceedings of the Proceedings 40th Annual Simulation Symposium (ANSS-40 2007), 2007