Alexandru Amaricai

Orcid: 0000-0002-2706-1781

According to our database1, Alexandru Amaricai authored at least 47 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2020
Layered LDPC decoder in-order message access scheduling: a case study.
Proceedings of the 14th IEEE International Symposium on Applied Computational Intelligence and Informatics, 2020

2019
Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Log-Likelihood Ratio based Generalized Belief Propagation.
Proceedings of the IEEE EUROCON 2019, 2019

Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
On the Redundant Representation of Partial Remainders in Radix-4 SRT Dividers.
J. Circuits Syst. Comput., 2017

Unrolled layered architectures for non-surjective finite alphabet iterative decoders.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Variable throughput LDPC decoders using SIMD-based adaptive quantization.
Proceedings of the 39th International Conference on Telecommunications and Signal Processing, 2016

Configurable FPGA architecture for hardware-software merge sorting.
Proceedings of the 2016 MIXDES, 2016

Reliability analysis of memory centric LDPC decoders under probabilistic storage failures.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
Generation of floating point 2D translation operators for FPGA.
Proceedings of the 10th IEEE Jubilee International Symposium on Applied Computational Intelligence and Informatics, 2015

Sub-threshold CMOS circuits reliability assessment using simulated fault injection based on simulator commands.
Proceedings of the 10th IEEE Jubilee International Symposium on Applied Computational Intelligence and Informatics, 2015

FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Direct FPGA-based power profiling for a RISC processor.
Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015

Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Template-based QC-LDPC decoder architecture generation.
Proceedings of the 10th International Conference on Information, 2015

2014
Low-precision DSP-based floating-point multiply-add fused for field programmable gate arrays.
IET Comput. Digit. Tech., 2014

Energy profiling of FPGA designs.
Proceedings of the 2014 IEEE International Symposium on Robotic and Sensors Environments, 2014

Cost effective FPGA probabilistic fault emulation.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Memory efficient implementation of self-corrected min-sum LDPC decoder.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

An FPGA sliding window-based architecture harris corner detector.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
SRT radix-2 dividers with (5, 4) redundant representation of partial remainder.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

FPGA implementation of hybrid fixed point - Floating point multiplication.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

2012
A cycle-count-accurate simulation platform with enhanced design exploration capability.
Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012

Automatic Generation of FPGA Hardware Accelerators for Graphics Applications.
Proceedings of the PECCS 2012, 2012

FPGA implementation of very high radix square root with prescaling.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Models and implementations of hardware interface modules in a multi-processor system-on-chip simulator.
Proceedings of the 6th IEEE International Symposium on Applied Computational Intelligence and Informatics, 2011

2010
Design Issues and Implementations for Floating-Point Divide-Add Fused.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Quantum circuit's reliability assessment with VHDL-based simulated fault injection.
Microelectron. Reliab., 2010

2009
Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Floating point multiplication rounding schemes for interval arithmetic.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
Simulated Fault Injection for Quantum Circuits Based on Simulator Commands.
Proceedings of the 4th International Symposium on Applied Computational Intelligence and Informatics, 2007

Assessing quantum circuits reliability with mutant-based simulated fault injection.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits.
Proceedings of the Proceedings 40th Annual Simulation Symposium (ANSS-40 2007), 2007


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