Tse-Yu Yeh

According to our database, Tse-Yu Yeh authored at least 14 papers between 1991 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor.

Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe

IEEE Micro, 2016

2014

Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache.

Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt

Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

2006

Low-power, high-performance architecture of the PWRficient processor family.

Tse-Yu Yeh

Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

2001

Understanding branches and designing branch predictors for high-performance microprocessors.

Marius Evers, Tse-Yu Yeh

Proc. IEEE, 2001

1998

Alternative Implementations of Two-Level Adaptive Branch Prediction.

Tse-Yu Yeh, Yale N. Patt

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction.

Tse-Yu Yeh, Yale N. Patt

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

1994

Branch classification: a new mechanism for improving branch predictor performance.

Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt

Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

1993

Two-level adaptive branch prediction and instruction fetch mechanisms for high performance superscalar processors.

Tse-Yu Yeh

PhD thesis, 1993

Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors.

Tse-Yu Yeh, Yale N. Patt

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History.

Tse-Yu Yeh, Yale N. Patt

Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache.

Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt

Proceedings of the 7th international conference on Supercomputing, 1993

1992

A comprehensive instruction fetch mechanism for a processor supporting speculative execution.

Tse-Yu Yeh, Yale N. Patt

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

1991

Two-Level Adaptive Training Branch Prediction.

Tse-Yu Yeh, Yale N. Patt

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

Single Instruction Stream Parallelism is Greater Than Two.

Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow

Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991