Tuomas Järvinen

According to our database, Tuomas Järvinen authored at least 15 papers between 2001 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2006

Software Pipelining Support for Transport Triggered Architecture Processors.

Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala

Proceedings of the Embedded Computer Systems: Architectures, 2006

Evaluation of stride permutation networks.

Tuomas Järvinen, Perttu Salmela, Konsta Punkka, Jarmo Takala

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Systematic approach for path metric access in Viterbi decoders.

Tuomas Järvinen, Perttu Salmela, Teemu Sipilä, Jarmo Takala

IEEE Trans. Commun., 2005

Efficient byte permutation realizations for compact AES implementations.

Tuomas Järvinen, Perttu Salmela, Panu Hämäläinen, Jarmo Takala

Proceedings of the 13th European Signal Processing Conference, 2005

256-State Rate 1/2 Viterbi Decoder on TTA Processor.

Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

Systematic methods for designing stride permutation interconnections.

Tuomas Järvinen

PhD thesis, 2004

Register-Based Permutation Networks for Stride Permutations.

Tuomas Järvinen, Jarmo Takala

Proceedings of the Computer Systems: Architectures, 2004

Stride Permutation Networks for Array Processors.

Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala

Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003

In-Place Storage of Path Metrics in Viterbi Decoders.

Tuomas Järvinen, Perttu Salmela, Teemu Sipilä, Jarmo Takala

Proceedings of the IFIP VLSI-SoC 2003, 2003

Parallel memory access in turbo decoders.

Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala

Proceedings of the IEEE 14th International Symposium on Personal, 2003

On allocation of turbo decoder iterations.

Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala

Proceedings of the IEEE 14th International Symposium on Personal, 2003

Conflict-free parallel memory access scheme for FFT processors.

Jarmo Takala, Tuomas Järvinen, Harri Sorokin

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Register-based reordering networks for matrix transpose.

Jarmo Takala, Tuomas Järvinen, Jari Nikara

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

Register-based multi-port perfect shuffle networks.

Tuomas Järvinen, Jarmo Takala, David Akopian, Jukka Saarinen

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Multi-port interconnection networks for radix-R algorithms.

Jarmo Takala, Tuomas Järvinen, Perttu Salmela, David Akopian

Proceedings of the IEEE International Conference on Acoustics, 2001