Perttu Salmela

According to our database1, Perttu Salmela authored at least 23 papers between 2001 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
Design Methodology for Offloading Software Executions to FPGA.
Signal Processing Systems, 2011

Fixed- versus floating-point implementation of MIMO-OFDM detector.
Proceedings of the IEEE International Conference on Acoustics, 2011

2009
3G Long Term Evolution Baseband Processing with Application-Specific Processors.
Int. J. Digital Multimedia Broadcasting, 2009

Reconfigurable video decoder with transform acceleration.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

2008
A Programmable Max-Log-MAP Turbo Decoder Implementation.
VLSI Design, 2008

Low-complexity polynomials modulo integer with linearly incremented variable.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Complex-valued QR decomposition implementation for MIMO receivers.
Proceedings of the IEEE International Conference on Acoustics, 2008

2007
Stride Permutation Networks for Array Processors.
VLSI Signal Processing, 2007

Application-Specific Instruction Set Processor Implementation of List Sphere Detector.
EURASIP J. Emb. Sys., 2007

Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Memory-Based List Updating for List Sphere Decoders.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Efficient parallel memory organization for turbo decoders.
Proceedings of the 15th European Signal Processing Conference, 2007

2006
Software Pipelining Support for Transport Triggered Architecture Processors.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Evaluation of stride permutation networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Systematic approach for path metric access in Viterbi decoders.
IEEE Trans. Communications, 2005

Efficient byte permutation realizations for compact AES implementations.
Proceedings of the 13th European Signal Processing Conference, 2005

256-State Rate 1/2 Viterbi Decoder on TTA Processor.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Complex Fixed-Point Matrix Inversion Using Transport Triggered Architecture.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2003
In-Place Storage of Path Metrics in Viterbi Decoders.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Parallel memory access in turbo decoders.
Proceedings of the IEEE 14th International Symposium on Personal, 2003

On allocation of turbo decoder iterations.
Proceedings of the IEEE 14th International Symposium on Personal, 2003

2001
Multi-port interconnection networks for radix-R algorithms.
Proceedings of the IEEE International Conference on Acoustics, 2001


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