Tyler L. Brandon

According to our database1, Tyler L. Brandon authored at least 13 papers between 2001 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2012
Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

2010
Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008
Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A scalable LDPC decoder ASIC architecture with bit-serial message exchange.
Integr., 2008

A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Design and Test of a 175-Mb/s, Rate-1/2 (128, 3, 6) Low-Density Parity-Check Convolutional Code Encoder and Decoder.
IEEE J. Solid State Circuits, 2007

2006
Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Efficient Encoding and Termination of Low-Density Parity-Check Convolutional Codes.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005
Design of a 3-D fully depleted SOI computational RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Test and Characterization of a Variable-Capacity Multilevel DRAM.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2001
Design of an Embedded Fully-Depleted SOI SRAM.
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001


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