Duncan G. Elliott

According to our database1, Duncan G. Elliott authored at least 41 papers between 1999 and 2020.

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Bibliography

2020
Analytic Model for Low Earth Orbit Satellite Solar Power.
IEEE Trans. Aerosp. Electron. Syst., 2020

2019
A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Design and Verification of a Robust Release Mechanism for CubeSat Deployables.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

2018
High-Efficiency Charge Pumps for Low-Power On-Chip Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Frequency Synthesis Based on A Novel Differential Locking Mechanism.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016
Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Design, evaluation and fault-tolerance analysis of stochastic FIR filters.
Microelectron. Reliab., 2016

HV-CMOS single-chip electronics platform for lab-on-chip DNA analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Coresidual alias-locked loops.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Design and evaluation of stochastic FIR filters.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

Stochastic circuit design and performance evaluation of vector quantization.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2013
A 6.0-13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
Deeply Pipelined Digit-Serial LDPC Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Effects of Varying Message Precision in Digit-Online LDPC Decoders.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

2011
Design and Characterization of a Multilevel DRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

High-Voltage CMOS Controller for Microfluidics.
IEEE Trans. Biomed. Circuits Syst., 2009

2008
Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A scalable LDPC decoder ASIC architecture with bit-serial message exchange.
Integr., 2008

Low-power static and dynamic high-voltage CMOS level-shifter circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An alias-locked loop frequency synthesis architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Clock-Logic Domino Circuits for High-Speed and Energy-Efficient Microprocessor Pipelines.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Design and Test of a 175-Mb/s, Rate-1/2 (128, 3, 6) Low-Density Parity-Check Convolutional Code Encoder and Decoder.
IEEE J. Solid State Circuits, 2007

2006
Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Efficient Encoding and Termination of Low-Density Parity-Check Convolutional Codes.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005
Design of a 3-D fully depleted SOI computational RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Test and Characterization of a Variable-Capacity Multilevel DRAM.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2003
Aliasing and anti-aliasing in branch history table prediction.
SIGARCH Comput. Archit. News, 2003

A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

An Investigation into Crosstalk Noise in DRAM Structures.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

2001
Design of an Embedded Fully-Depleted SOI SRAM.
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

1999
Fault Models and Tests for a 2-Bit-per-Cell MLDRAM.
IEEE Des. Test Comput., 1999

Computational RAM: Implementing Processors in Memory.
IEEE Des. Test Comput., 1999

A Comparative Simulation Study of Four Multilevel DRAMs.
Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999


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