Vincent C. Gaudet

According to our database1, Vincent C. Gaudet authored at least 72 papers between 1998 and 2019.

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Bibliography

2019

2018
Multi-Module Range Anxiety Reduction Scheme for Battery-Powered Vehicles.
Proceedings of the 2018 IEEE Intelligent Vehicles Symposium, 2018

Efficient Hardware Realization of Convolutional Neural Networks Using Intra-Kernel Regular Pruning.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

2017
On the Fault Tolerance of Stochastic Decoders.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

2016
Guest Editorial Emerging Topics in Multiple-Valued Logic and Its Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

A Survey and Tutorial on Contemporary Aspects of Multiple-Valued Logic and Its Application to Microelectronic Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

HV-CMOS single-chip electronics platform for lab-on-chip DNA analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 16-bit high-speed low-power hybrid adder.
Proceedings of the 28th International Conference on Microelectronics, 2016

2015
VLSI implementation of high-throughput, low-energy, configurable MIMO detector.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A hybrid ARQ scheme using LDPC codes with stochastic decoding.
Proceedings of the 49th Annual Conference on Information Sciences and Systems, 2015

A low-latency algorithm for stochastic decoding of LDPC codes.
Proceedings of the 53rd Annual Allerton Conference on Communication, 2015

Trapping sets in stochastic LDPC decoders.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model.
J. Signal Process. Syst., 2014

High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model.
IEICE Trans. Inf. Syst., 2014

FPGA implementation of a clockless stochastic LDPC decoder.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Neural Spike Compression Using Feature Extraction and a Fuzzy C-Means Codebook.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Adaptive dual-threshold neural signal compression suitable for implantable recording.
Proceedings of the IEEE International Conference on Acoustics, 2014

Output decisions for stochastic LDPC decoders.
Proceedings of the 48th Annual Conference on Information Sciences and Systems, 2014

2013
Log-Domain Arithmetic for High-Speed Fuzzy Control on a Field-Programmable Gate Array.
Proceedings of the Soft Computing: State of the Art Theory and Novel Applications, 2013

DS-CDMA Implementation With Iterative Multiple Access Interference Cancellation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

High-throughput CAM based on a synchronous overlapped search scheme.
IEICE Electron. Express, 2013

Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

A scaling method for stochastic LDPC decoding over the binary symmetric channel.
Proceedings of the 47th Annual Conference on Information Sciences and Systems, 2013

2012
Switching Activity Minimization in Iterative LDPC Decoders.
J. Signal Process. Syst., 2012

Design of a Low Power, Inductorless Wideband Variable-Gain Amplifier for High-Speed Receiver Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Deeply Pipelined Digit-Serial LDPC Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Clockless Stochastic Decoding of Low-Density Parity-Check Codes.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Effects of Varying Message Precision in Digit-Online LDPC Decoders.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011
Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Hardware implementation challenges of modern error control decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A Markov chain model for Edge Memories in stochastic decoding of LDPC codes.
Proceedings of the 45st Annual Conference on Information Sciences and Systems, 2011

2010
Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Relaxation dynamics in stochastic iterative decoders.
IEEE Trans. Signal Process., 2010

Scaling of analog LDPC decoders in sub-100 nm CMOS processes.
Integr., 2010

Switching Activity in Stochastic Decoders.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

Implementation of enhanced CDMA utilizing low complexity joint detection with iterative processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Analog DFT Processors for OFDM Receivers: Circuit Mismatch and System Performance Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A dual-function mixed-signal circuit for LDPC encoding/decoding.
Integr., 2009

High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving.
IEICE Trans. Electron., 2009

Design of a High-Speed Fuzzy Logic Controller Based on Log-Domain Arithmetic.
Proceedings of the ISMVL 2009, 2009

An Asynchronous Programmable Parallel 2-D Image Filter CMOS Ic Based on the Gilbert Vector Multiplier.
Proceedings of the BIODEVICES 2009, 2009

2008
A CMOS IR-UWB Transceiver Design for Contact-Less Chip Testing Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A scalable LDPC decoder ASIC architecture with bit-serial message exchange.
Integr., 2008

A cache-based internet protocol address lookup architecture.
Comput. Networks, 2008

Low-power static and dynamic high-voltage CMOS level-shifter circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Current-mode memory cell with power down phase for discrete time analog iterative decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Design for Testability of CMOS Analog Sum-Product Error-Control Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Inductive ESD Protection For Narrow Band and Ultra-Wideband CMOS Low Noise Amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Low-voltage CMOS circuits for analog iterative decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Degree-Matched Check Node Decoding for Regular and Irregular LDPCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Analysis of error control code use in ultra-low-power wireless sensor networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Soft-bit decoding of regular low-density parity-check codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

On Multiple Slice Turbo Codes.
Ann. des Télécommunications, 2005

A Multizone Pipelined Cache for IP Routing.
Proceedings of the NETWORKING 2005: Networking Technologies, 2005

A Tier 3 Software Defined AM Radio.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Stochastic iterative decoders.
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005

A degree-matched check node approximation for LDPC decoding.
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005

Digital built-in self-test of CMOS analog iterative decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A hardware-based longest prefix matching scheme for TCAMs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An analog/digital mode-switching LDPC codec.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Short-cycle-free interleaver design for increasing minimum squared Euclidean distance.
Proceedings of the 2004 IEEE International Symposium on Information Theory, 2004

A 0.8V CMOS analog decoder for an (8, 4, 4) extended Hamming code.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

1998
Implementation Issues for High-Bandwidth Field-Programmable Analog Arrays.
J. Circuits Syst. Comput., 1998


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