Umanath Kamath

Orcid: 0000-0001-7536-3576

According to our database1, Umanath Kamath authored at least 6 papers between 2017 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2021
Reference Voltage Buffer for Hybrid RC-DAC SAR ADCs in 130 nm CMOS Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Read-Out Architecture of CRYO System-on-Chip ASIC for Noble Liquid TPC Detectors.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
A 1-V Bandgap Reference in 7-nm FinFET With a Programmable Temperature Coefficient and Inaccuracy of ±0.2% From -45°C to 125°C.
IEEE J. Solid State Circuits, 2019

2018
BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFET.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from -45°C to 125°C.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017


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