Asma Laraba

According to our database, Asma Laraba authored at least 9 papers between 2012 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET.

Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans

IEEE J. Solid State Circuits, 2022

2021

A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET.

Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2018

A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.

James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017

16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC.

Bruno Vaz, Adrian Lynam, Bob Verbruggen, Asma Laraba, Conrado Mesadri, Ali Boumaalif, John McGrath, Umanath Kamath, Ronnie De La Torre, Alvin Manlapat, Daire Breathnach, Christophe Erdmann, Brendan Farley

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs.

Guillaume Renaud, Manuel J. Barragán, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet

J. Electron. Test., 2016

2015

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique.

Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2013

Reduced-Code Linearity Testing of Pipeline ADCs.

Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret

IEEE Des. Test, 2013

Reduced code linearity testing of pipeline adcs in the presence of noise.

Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012

Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs.

Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Christophe Forel

Proceedings of the 17th IEEE European Test Symposium, 2012