Christophe Erdmann

According to our database1, Christophe Erdmann authored at least 12 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters.
IEEE Open J. Circuits Syst., 2021

A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A Wideband 6th Order Programmable Bandpass DEM Implementation for a Nyquist DAC.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2018
An All-Programmable 16-nm RFSoC for Digital-RF Communications.
IEEE Micro, 2018


A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A programmable RFSoC in 16nm FinFET technology for wideband communications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2015
A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters.
IEEE J. Solid State Circuits, 2015

2014
6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014


  Loading...