Venkataraman Mahalingam

According to our database1, Venkataraman Mahalingam authored at least 15 papers between 2003 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2012
Dynamic clock stretching for variation compensation in VLSI circuit design.
ACM J. Emerg. Technol. Comput. Syst., 2012

2010
Timing-Based Placement Considering Uncertainty Due to Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
Variation-aware multimetric optimization during gate sizing.
ACM Trans. Design Autom. Electr. Syst., 2009

A VLSI System Architecture for Optical Flow Computation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Variation Aware Timing Based Placement Using Fuzzy Programming.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition.
IEEE Trans. Computers, 2006

An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A novel approach for variation aware power minimization during gate sizing.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

2004
Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003
Analysis of Bit Transition Count for EDAC Encoded FSM.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003


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