Victor V. Zhirnov

According to our database, Victor V. Zhirnov authored at least 13 papers between 2001 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Nurturing the Growth of a National Infrastructure in Emerging Technologies.

Rafic Z. Makki, Victor V. Zhirnov, Ralph K. Cavin III, Sami Issa, Marco Iansiti

Proc. IEEE, 2018

2012

Science and Engineering Beyond Moore's Law.

Ralph K. Cavin III, Paolo Lugli, Victor V. Zhirnov

Proc. IEEE, 2012

Prolog to the Section on Science and Engineering Beyond Moore's Law.

Ralph K. Cavin III, Paolo Lugli, Victor V. Zhirnov

Proc. IEEE, 2012

2010

Memory Devices: Energy-Space-Time Tradeoffs.

Victor V. Zhirnov, Ralph K. Cavin III, Stephan Menzel, Eike Linn, Sebastian Schmelzer, Dennis Bräuhaus, Christina Schindler, Rainer Waser

Proc. IEEE, 2010

2009

Scaling beyond CMOS: Turing-Heisenberg Rapproachment.

Victor V. Zhirnov, Ralph K. Cavin III

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008

An Assessment of Integrated Digital Cellular Automata Architectures.

Victor V. Zhirnov, Ralph K. Cavin III, Greg Leeming, Kosmas Galatsis

Computer, 2008

Emerging Nanoscale Memory and Logic Devices: A Critical Assessment.

James A. Hutchby, Ralph K. Cavin III, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff

Computer, 2008

Emerging Research Architectures.

Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff

Computer, 2008

Boolean Logic and Alternative Information-Processing Devices.

George Bourianoff, Joe E. Brewer, Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov

Computer, 2008

The Viability of Cellular Automata Architectures for General Purpose Computing.

Victor V. Zhirnov, Greg Leeming, Kosmas Galatsis, Ralph K. Cavin III

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2005

Future devices for information processing.

Ralph K. Cavin III, Victor V. Zhirnov

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2003

Limits to binary logic switch scaling - a gedanken model.

Victor V. Zhirnov, Ralph K. Cavin III, James A. Hutchby, George Bourianoff

Proc. IEEE, 2003

2001

New Frontiers: Self-Assembly and Nanoelectronics.

Victor V. Zhirnov, Daniel J. C. Herr

Computer, 2001