Vijay Rentala

According to our database1, Vijay Rentala authored at least 10 papers between 2001 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021

2019

2018

2014
A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS.
IEEE J. Solid State Circuits, 2014

2013

2012
Low power ADC's for wireless communications.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2010
A 1.16mW 69dB SNR (1.2MHz BW) continuous time £Δ ADC with immunity to clock jitter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2005
A 700+-mW class D design with direct battery hookup in a 90-nm process.
IEEE J. Solid State Circuits, 2005

2004
A 250 mW class D design with direct battery hookup in a 90 nm process [audio band switching amplifier].
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2001
A constant GM rail-to-rail opamp with a novel input stage for BiCMOS process.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001


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