Marco Corsi

According to our database¹, Marco Corsi authored at least 13 papers between 2003 and 2021.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Awards

IEEE Fellow

IEEE Fellow 2013, "For development of high-speed amplifiers and analog to-digital convertors".

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2021

F2: Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Session 10 Overview: Continuous-Time ADCs and DACs Data Converter Subcommittee.

[BibT_eX]

[DOI]

Seyfi S. Bazarjani

Jongwoo Lee

Marco Corsi

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

CLC+ Backbone: Set the Scene in Copernicus for the Coming Decade.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2021

2018

Geolocating social media posts for emergency mapping.

[BibT_eX]

[DOI]

Mariano Alfonso Biscardi

CoRR, 2018

2013

Applicability of MPLS Transport Profile for Ring Topologies.

[BibT_eX]

[DOI]

RFC, July, 2013

2012

Low power ADC's for wireless communications.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 20mW 61dB SNDR (60MHz BW) 1b 3<sup>rd</sup>-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling.

[BibT_eX]

[DOI]

Kailash Chandrashekar

Marco Corsi

John W. Fattaruso

Bertan Bakkaloglu

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A 16b 100-to-160MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDR.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2003

A 610-mW zero-overhead class-G full-rate ADSL CO line driver.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

An ADSL integrated active hybrid circuit.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2003, 2003

Marco Corsi

Awards

IEEE Fellow

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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