Vijay Sundararajan

According to our database1, Vijay Sundararajan authored at least 20 papers between 1997 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
Gate Sizing.
Encyclopedia of Algorithms, 2016

2008
Gate Sizing.
Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Optimal power allocation for sum capacity of a slotted three-cell system.
Proceedings of the IEEE International Conference on Acoustics, 2008

2004
A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints.
ACM Trans. Design Autom. Electr. Syst., 2004

2003
Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems.
IEEE Trans. Signal Processing, 2003

2002
Fast and exact transistor sizing based on iterative relaxation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

2001
Vector processing of wavelet coefficients for robust image denoising.
Image Vis. Comput., 2001

Energy Efficient Signaling in Deep Submicron CMOS Technology.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Energy efficient signaling in DSM CMOS technology.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A novel multiply multiple accumulator component for low power PDSP design.
Proceedings of the IEEE International Conference on Acoustics, 2000

Reducing bus transition activity by limited weight coding with codeword slimming.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

MINFLOTRANSIT: min-cost flow based transistor sizing tool.
Proceedings of the 37th Conference on Design Automation, 2000

Data transmission over a bus with peak-limited transition activity.
Proceedings of ASP-DAC 2000, 2000

Synthesis of low power folded programmable coefficient FIR digital filters (short paper).
Proceedings of ASP-DAC 2000, 2000

1999
Low power synthesis of dual threshold voltage CMOS VLSI circuits.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Marsh: min-area retiming with setup and hold constraints.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages.
Proceedings of the 36th Conference on Design Automation, 1999

Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1998
Synthesis of folded, pipelined architectures for multi-dimensional multirate systems.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997
A Wavelet-Domain Algorithm for Denoising in the Presence of Noise Outliers.
Proceedings of the Proceedings 1997 International Conference on Image Processing, 1997


  Loading...