C. P. Ravikumar

According to our database1, C. P. Ravikumar authored at least 112 papers between 1987 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Industrial Practices in Low-Power Robust Design.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

2018
Architectural Optimization of Hierarchically Organized Wireless Sensor Networks for Energy, Cost, and Security.
J. Low Power Electron., 2018

2016
Smart and Fault-Tolerant LED-Based Street Lamps.
J. Low Power Electron., 2016

2013
Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation
CoRR, 2013

2012
On-chip memory architecture exploration framework for DSP processor-based embedded system on chip.
ACM Trans. Embed. Comput. Syst., 2012

2008
Test Strategies for Low-Power Devices.
J. Low Power Electron., 2008

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction.
J. Low Power Electron., 2008

Memory Architecture Exploration Framework for Cache Based Embedded SOC.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
A critical-path-aware partial gating approach for test power reduction.
ACM Trans. Design Autom. Electr. Syst., 2007

Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Low-Power Hierarchical Scan Test for Multiple Clock Domains.
J. Low Power Electron., 2007

Conference Reports.
IEEE Des. Test Comput., 2007

Variation-Tolerant, Power-Safe Pattern Generation.
IEEE Des. Test Comput., 2007

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test.
Proceedings of the 2007 IEEE International Test Conference, 2007

A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test.
Proceedings of the 2007 IEEE International Test Conference, 2007

Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides.
Proceedings of the 16th Asian Test Symposium, 2007

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores.
J. Low Power Electron., 2006

Conference Reports.
IEEE Des. Test Comput., 2006

2005
At-Speed Transition Fault Testing With Low Speed Scan Enable.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A Framework for Distributed and Hierarchical Design-for-Test.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Enhanced launch-off-capture transition fault testing.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Partial Gating Optimization for Power Reduction During Test Application.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
A self-checking signature scheme for checking backdoor security attacks in Internet.
J. High Speed Networks, 2004

Multiprocessor Architectures for Embedded System-on-chip Applications.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Holistic Parallel and Hierarchical Approach towards Design-For-Test.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Mutual Testing based on Wavelet Transforms.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Optimal Code and Data Layout in Embedded Systems.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Static Verification of Test Vectors for IR Drop Failure.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
Improvement of ASIC Design Processes.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Divide-and-Conquer IDDQ Testing for Core-Based System Chips.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

An Evolutionary Scheme for Cosynthesis of Real-Time Systems.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Measuring the Quality of Web Search Results.
Proceedings of the 6th Joint Conference on Information Science, 2002

2001
Distributed Fault Simulation Algorithms on Parallel Virtual Machine.
VLSI Design, 2001

Estimating Crosstalk From Vlsi Layouts.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Software Power Optimizations In An Embedded System.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000
A scheme for multiple on-chip signature checking for embedded SRAMS.
J. Syst. Archit., 2000

Efficient Implementation of ADPCM Codec.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A Stochastic Framework for Co-synthesis of Real-Time Systems.
Proceedings of the Languages, 2000

Functional Testing of Microprocessors with Graded Fault Coverage.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
High-Performance Cluster Computing. Volume 1: Architecutes and Systems. Volume 2: Programming and Applications.
Parallel Distributed Comput. Pract., 1999

A functional-level testability measure for register-level circuits and its estimation.
Microprocess. Microsystems, 1999

Built-in Self Test Based on Multiple On-Chip Signature Checking.
J. Electron. Test., 1999

Improving the Diagnosability of Digital Circuits.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Hierarchical Delay Fault Simulation.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Design of WDM Networks for Delay-Bound Multicasting.
Proceedings of the High Performance Computing, 1999

Efficient Algorithms for Delay Bounded Multicast Tree Generation for Multimedia Applications.
Proceedings of the High Performance Computing, 1999

Design Issues in Synthesis of Reusable Cores.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
Testability-Driven Layout of Combinational Circuits.
VLSI Design, 1998

SCOAP-based Testability Analysis from Hierarchical Netlists.
VLSI Design, 1998

Parallel Methods for Vlsi Layout Design.
IEEE Concurr., 1998

Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems.
J. Electron. Test., 1998

Source-based delay-bounded multicasting in multimedia networks.
Comput. Commun., 1998

Freedom: Statistical Behavioral Estimation of System Energy and Power.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Synthesis of Testable RTL Designs.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

An Evolutionary Approach to System Redesign.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

On-Chip Signature Checking for Embedded Memories.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Hybrid Testing Schemes Based on Mutual and Signature Testing.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Performance-driven design and redesign of high-speed local area networks.
Proceedings of the 5th International Conference On High Performance Computing, 1998

Efficient algorithms for delay-bounded minimum cost path problem in communication networks.
Proceedings of the 5th International Conference On High Performance Computing, 1998

Adaptive Routing Based on Deadlock Recovery.
Proceedings of the Euro-Par '98 Parallel Processing, 1998

Evaluating BIST Architectures for Low Power.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Adaptive routing in k-ary n-cubes using incomplete diagnostic information.
Microprocess. Microsystems, 1997

Parallelization of symmetry detection algorithms on a network of workstations.
Microprocess. Microsystems, 1997

Hierarchical Delay Test Generation.
J. Electron. Test., 1997

Kautz graphs as attractive logical topologies in multihop lightwave networks.
Comput. Commun., 1997

Faster Fault Simulation Through Distributed Computing.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Graph-Theoretic Approach for Register File Based Synthesis.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Rapid Synthesis of Multi-Chip Systems.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Efficient Implementation of Multiple On-Chip Signature Checking.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

An Euler Path Based Technique for Deadlock-free Multicasting.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

Distributed delay constrained multicast path setup algorithm for high speed networks.
Proceedings of the Fourth International on High-Performance Computing, 1997

1996
TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis.
VLSI Design, 1996

Parallel search-and-learn techniques and graph coloring.
Knowl. Based Syst., 1996

Fault-tolerant routing in multiply twisted cube topology.
J. Syst. Archit., 1996

Synthesis of Testable Pipelined Datapaths Using Genetic Search.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Genetic Algorithms for Scan Path Design.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Estimation of Power from Module-level Netlists.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Novel BIST Architecture With Built-in Self Check.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A genetic algorithm for assembling optical computers using faulty optical arrays.
Proceedings of the 3rd International Conference on High Performance Computing, 1996

Efficient Delay Test Generation for Modular Circuits.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995
SHARP: A shape recognition system and its parallel implementation.
Microprocess. Microsystems, 1995

Heuristic and neural algorithms for mapping tasks to a reconfigurable array.
Microprocess. Microprogramming, 1995

HISCOAP: a hierarchical testability analysis tool.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A STAFAN-like functional testability measure for register-level circuits.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing.
VLSI Design, 1994

Parallel search-and-learn technique for solving large scale travelling-salesperson problems.
Knowl. Based Syst., 1994

Simulated Annealing for Target-Oriented Scan.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Star-Graph based multistage interconnection network for ATM switch fabric.
Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994

1993
Solving VLSI physical design problems on a vector machine.
Comput. Aided Des., 1993

A Parallel Search-and-Learn Technique for Solving Large Scale TSP.
Proceedings of the Fifth International Conference on Tools with Artificial Intelligence, 1993

Incomplete Star Graph: An Economical Fault-tolerant Interconnection Network.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

1992
Parallel techniques for solving large scale travelling salesperson problems.
Microprocess. Microsystems, 1992

Interval partition with bounded overlap.
Comput. Aided Des., 1992

Solving Physical Design Problems on a Vector Machine.
Proceedings of the Fifth International Conference on VLSI Design, 1992

1991
VYUHA: A detailed router for multiple routing models.
Integr., 1991

1990
Performance improvement of simulated annealing algorithms.
Comput. Syst. Sci. Eng., 1990

1989
A hardware accelerator for hierarchical VLSI routing.
Integr., 1989

Parallel Placement on Hypercube Architecture.
Proceedings of the International Conference on Parallel Processing, 1989

1988
Parallel Placement on Reduced Array Architecture.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
An Architecture for CSP and Its Simulation.
Proceedings of the International Conference on Parallel Processing, 1987


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