Vinícius Dal Bem

According to our database, Vinícius Dal Bem authored at least 13 papers between 2010 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC.

Vinícius Dal Bem, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas

IEEE Trans. Emerg. Top. Comput., 2017

2016

SAT based environment for logical capacity evaluation of via configurable block templates.

Vinícius Dal Bem

PhD thesis, 2016

2013

BTI and HCI first-order aging estimation for early use in standard cell technology mapping.

Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas

Microelectron. Reliab., 2013

Analytical logical effort formulation for minimum active area under delay constraints.

Caio G. P. Alegretti, Vinícius Dal Bem, Renato P. Ribas, André Inácio Reis

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Logic synthesis for manufacturability considering regularity and lithography printability.

Lucas Machado, Vinícius Dal Bem, Francesc Moll, Sergio Gómez, Renato P. Ribas, André Inácio Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2012

Design of CMOS logic gates with enhanced robustness against aging degradation.

Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas

Microelectron. Reliab., 2012

Lithography analysis of via-configurable transistor-array fabrics.

Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas

Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2011

Transistor sizing in lithography-aware regular fabrics.

Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Francesc Moll, Renato P. Ribas

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Area impact analysis of via-configurable regular fabric for digital integrated circuit design.

Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Impact and optimization of lithography-aware regular layout in digital circuit design.

Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Transistor Sizing Analysis of Regular Fabrics.

Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas, Francesc Moll

Proceedings of the ARCS 2011, 2011

2010

Transistor network restructuring against NBTI degradation.

Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas

Microelectron. Reliab., 2010

Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits.

Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas

J. Low Power Electron., 2010