Francesc Moll

According to our database1, Francesc Moll authored at least 43 papers between 2002 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Mechanical Energy Harvesting Taxonomy for Industrial Environments: Application to the Railway Industry.
IEEE Trans. Intell. Transp. Syst., 2020

2019
Linear, Time-Invariant Model of the Dynamics of a CMOS CC-CP.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018
Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Comprehensive Method to Taxonomize Mechanical Energy Harvesting Technologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Insights Into Tunnel FET-Based Charge Pumps and Rectifiers for Energy Harvesting Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells.
Proceedings of the 14th International Conference on Synthesis, 2017

An on-line test strategy and analysis for a 1T1R crossbar memory.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016
Feasibility of Embedded DRAM Cells on FinFET Technology.
IEEE Trans. Computers, 2016

Experience on material implication computing with an electromechanical memristor emulator.
Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

A battery-less, self-sustaining RF energy harvesting circuit with TFETs for µW power applications.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

ASIC Implementation of An All-digital Self-adaptive PVTA Variation-aware Clock Generation System.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Local variations compensation with DLL-based Body Bias Generator for UTBB FD-SOI technology.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Tunnel FET device characteristics for RF energy harvesting passive rectifiers.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Novel charge pump converter with Tunnel FET devices for ultra-low power energy harvesting sources.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Novel UHF Passive Rectifier with Tunnel FET Devices.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Pespectives of TFET devices in ultra-low power charge pumps for thermo-electric energy sources.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET.
Microelectron. Reliab., 2014

2013
Systematic and random variability analysis of two different 6T-SRAM layout topologies.
Microelectron. J., 2013

A single event transient hardening circuit design technique based on strengthening.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Logic synthesis for manufacturability considering regularity and lithography printability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Variation tolerant self-adaptive clock generation architecture based on a ring oscillator.
Proceedings of the IEEE 25th International SOC Conference, 2012

Evaluation of layout design styles using a quality design metric.
Proceedings of the IEEE 25th International SOC Conference, 2012

PVTA Tolerant Self-adaptive Clock Generation Architecture.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2011
New redundant logic design concept for high noise and low voltage scenarios.
Microelectron. J., 2011

Design of complex circuits using the Via-Configurable transistor array regular layout fabric.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Monitor strategies for variability reduction considering correlation between power and timing variability.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Transistor sizing in lithography-aware regular fabrics.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

A new probabilistic design methodology of nanoscale digital circuits.
Proceedings of the CONIELECOMP 2011, 21st International Conference on Electrical, Communications, and Computers, 28 February, 2011

Transistor Sizing Analysis of Regular Fabrics.
Proceedings of the ARCS 2011, 2011

Design Guidelines towards Compact Litho-Friendly Regular cells.
Proceedings of the ARCS 2011, 2011

SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels.
Proceedings of the ARCS 2011, 2011

2010
Lithography Aware Regular Cell Design Based on a Predictive Technology Model.
J. Low Power Electron., 2010

VCTA: A Via-Configurable Transistor Array regular fabric.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

2009
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs.
Microelectron. J., 2009

2008
Data Dependence of Delay Distribution for a Planar Bus.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
Power supply noise and logic error probability.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2003
Analysis of dissipation energy of switching digital CMOS gates with coupled outputs.
Microelectron. J., 2003

Analysis of the Contribution of Interconnect Effects in the Energy Dissipation of VLSI Circuits.
Proceedings of the Integrated Circuit and System Design, 2003

2002
Noise Generation and Coupling Mechanisms in Deep-Submicron ICs.
IEEE Des. Test Comput., 2002


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