Paulo F. Butzen
Orcid: 0000-0003-1587-7596
According to our database1,
Paulo F. Butzen
authored at least 59 papers
between 2007 and 2023.
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Bibliography
2023
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems.
J. Electron. Test., August, 2023
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Integr., 2022
A Predictive Approach for Conditional Execution of Memristive Material Implication Stateful Logic Operations.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Evaluating Soft Error Reliability of Combinational Circuits Using a Monte Carlo Based Method.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions.
J. Electron. Test., 2021
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Proceedings of the IEEE Latin-American Test Symposium, 2020
Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients.
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Reduction of neural network circuits by constant and nearly constant signal propagation.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
Microelectron. Reliab., 2018
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
16NM 6T and 8T CMOS SRAM Cell Robustness Against Process Variability and Aging Effects.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
2016
Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters.
Microelectron. Reliab., 2016
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
An Incremental Timing-Driven flow using quadratic formulation for detailed placement.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
2013
BTI and HCI first-order aging estimation for early use in standard cell technology mapping.
Microelectron. Reliab., 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
2012
Microelectron. Reliab., 2012
2011
An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Area impact analysis of via-configurable regular fabric for digital integrated circuit design.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Impact and optimization of lithography-aware regular layout in digital circuit design.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
2010
Microelectron. Reliab., 2010
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits.
Microelectron. J., 2010
Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits.
J. Low Power Electron., 2010
2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
2008
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007