Renato P. Ribas

Pierre-Emmanuel Gaillardon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020

Parallel Combinational Equivalence Checking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

maj-n Logic Synthesis for Emerging Technology.

[BibT_eX]

[DOI]

Augusto Neutzling

Jody Maick Matos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Exact Benchmark Circuits for Logic Synthesis.

[BibT_eX]

[DOI]

Walter Lau Neto

Pierre-Emmanuel Gaillardon

Jody Maick Matos

Renato Perez Ribas

IEEE Des. Test, 2020

2019

Four-Level Forms for Memristive Material Implication Logic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Effective Logic Synthesis for Threshold Logic Circuit Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018

A Simple and Effective Heuristic Method for Threshold Logic Identification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.

[BibT_eX]

[DOI]

Walter Lau Neto

Jody Maick Matos

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Unlocking fine-grain parallelism for AIG rewriting.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC.

[BibT_eX]

[DOI]

Vinícius Dal Bem

IEEE Trans. Emerg. Top. Comput., 2017

Transistor Count Optimization in IG FinFET Network Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Binary adder circuit design using emerging MIGFET devices.

[BibT_eX]

[DOI]

Jeferson José Baqueta

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016

Graph-Based Transistor Network Generation Method for Supergate Design.

[BibT_eX]

[DOI]

Vinicius Neves Possani

IEEE Trans. Very Large Scale Integr. Syst., 2016

On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design.

[BibT_eX]

[DOI]

Proceedings of the 17th Latin-American Test Symposium, 2016

Performance evaluation of optimized transistor networks built using independent-gate FinFET.

[BibT_eX]

[DOI]

Andres M. A. Valdes

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015

Factored Forms for Memristive Material Implication Stateful Logic.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

MCML Gate Design for Standard Cell Library.

[BibT_eX]

[DOI]

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Open Cell Library in 15nm FreePDK Technology.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Fast buffer delay estimation considering time-dependent dielectric breakdown.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Improved logic synthesis for memristive stateful logic using multi-memristor implication.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Automatic circuit generation for sequential logic debug.

[BibT_eX]

[DOI]

Helder H. Avelar

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

SOP based logic synthesis for memristive IMPLY stateful logic.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Threshold Logic Synthesis Based on Cut Pruning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Enhanced Spin-Diode Synthesis Using Logic Sharing.

[BibT_eX]

[DOI]

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

Exploring Independent Gates in FinFET-Based Transistor Network Generation.

[BibT_eX]

[DOI]

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Deriving Reduced Transistor Count Circuits from AIGs.

[BibT_eX]

[DOI]

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Methodology for achieving best trade-off of area and fault masking coverage in ATMR.

[BibT_eX]

[DOI]

Iuri A. C. Gomes

Fernanda Lima Kastensmidt

Sylvain P. Novales

Proceedings of the 15th Latin American Test Workshop, 2014

A constructive approach for threshold logic circuit synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

CMOS inverter analytical delay model considering all operating regions.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013

BTI, HCI and TDDB aging impact in flip-flops.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2013

BTI and HCI first-order aging estimation for early use in standard cell technology mapping.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2013

Power consumption analysis in static CMOS gates.

[BibT_eX]

[DOI]

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Improving the methodology to build non-series-parallel transistor arrangements.

[BibT_eX]

[DOI]

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

A methodology to evaluate the aging impact on flip-flops performance.

[BibT_eX]

[DOI]

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Synthesis of threshold logic gates to nanoelectronics.

[BibT_eX]

[DOI]

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Spin diode network synthesis using functional composition.

[BibT_eX]

[DOI]

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Delay model for static CMOS complex gates.

[BibT_eX]

[DOI]

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Parallel prefix adder design using quantum-dot cellular automata.

[BibT_eX]

[DOI]

Kim A. Escobar

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Read-polarity-once Boolean functions.

[BibT_eX]

[DOI]

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Analytical logical effort formulation for minimum active area under delay constraints.

[BibT_eX]

[DOI]

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Transistor-level optimization of CMOS complex gates.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Iterative remapping respecting timing constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Logic synthesis for manufacturability considering regularity and lithography printability.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

CMOS inverter delay model based on DC transfer curve for slow input.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Efficient transistor-level design of CMOS gates.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Design of CMOS logic gates with enhanced robustness against aging degradation.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.

[BibT_eX]

[DOI]

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Design-oriented delay model for CMOS inverter.

[BibT_eX]

[DOI]

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

KL-cut based digital circuit remapping.

[BibT_eX]

[DOI]

Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Lithography analysis of via-configurable transistor-array fabrics.

[BibT_eX]

[DOI]

Vinícius Dal Bem

Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Functional composition: A new paradigm for performing logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

Contributions to the evaluation of ensembles of combinational logic gates.

[BibT_eX]

[DOI]

Microelectron. J., 2011

Ring oscillators for functional and delay test of latches and flip-flops.

[BibT_eX]

[DOI]

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Transistor sizing in lithography-aware regular fabrics.

[BibT_eX]

[DOI]

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Area impact analysis of via-configurable regular fabric for digital integrated circuit design.

[BibT_eX]

[DOI]

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Constructive AIG optimization considering input weights.

[BibT_eX]

[DOI]

Thiago Figueiro

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Self-checking test circuits for latches and flip-flops.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Performance and functional test of flip-flops using ring oscillator structure.

[BibT_eX]

[DOI]

André Ivanov

Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Impact and optimization of lithography-aware regular layout in digital circuit design.

[BibT_eX]

[DOI]

Vinícius Dal Bem

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Efficient method to compute minimum decision chains of Boolean functions.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Transistor Sizing Analysis of Regular Fabrics.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2011, 2011

Constructive AIG optimization through functional composition.

[BibT_eX]

[DOI]

Thiago Figueiro

Proceedings of the ARCS 2011, 2011

SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2011, 2011

2010

Karma: um ambiente para o aprendizado de síntese de funções Booleanas.

[BibT_eX]

[DOI]

Carlos Eduardo Klock

Renato Perez Ribas

Revista Brasileira de Informática na Educ., 2010

Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology.

[BibT_eX]

[DOI]

Digeorgia N. da Silva

Microelectron. Reliab., 2010

Transistor network restructuring against NBTI degradation.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2010

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits.

[BibT_eX]

[DOI]

Erasmo J. D. Chiappetta Filho

Microelectron. J., 2010

Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2010

Improvements on the detection of false paths by using unateness and satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

SwitchCraft: a framework for transistor network design.

[BibT_eX]

[DOI]

Carlos Eduardo Klock

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Boolean factoring with multi-objective goals.

[BibT_eX]

[DOI]

Anders B. Rasmussen

Proceedings of the 28th International Conference on Computer Design, 2010

KL-Cuts: A new approach for logic synthesis targeting multiple output blocks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

CMOS logic gate performance variability related to transistor network arrangements.

[BibT_eX]

[DOI]

Digeorgia N. da Silva

Microelectron. Reliab., 2009

Routing Resistance Influence in Loading Effect on Leakage Analysis.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Switch level optimization of digital CMOS gate networks.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Efficient Test Circuit to Qualify Logic Cells.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.

[BibT_eX]

[DOI]

Tiago Muller Gil Cardoso

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.

[BibT_eX]

[DOI]

Erasmo J. D. Chiappetta Filho

Dionatan S. Moura

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

A comparative study of CMOS gates with minimum transistor stacks.

[BibT_eX]

[DOI]

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

KARMA: A Didactic Tool for Two-Level Logic Synthesis.

[BibT_eX]

[DOI]

Carlos Eduardo Klock

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Modeling Subthreshold Leakage Current in General Transistor Networks.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

DAG based library-free technology mapping.

[BibT_eX]

[DOI]

Sachin S. Sapatnekar

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Modeling and estimating leakage current in series-parallel CMOS networks.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Fast disjoint transistor networks from BDDs.

[BibT_eX]

[DOI]

Tiago Muller Gil Cardoso

Sachin S. Sapatnekar

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Asynchronous circuit design on reconfigurable devices.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

2005

Exact lower bound for the number of switches in series to implement a combinational logic cell.

[BibT_eX]

[DOI]

Sachin S. Sapatnekar

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Tool integration using the web-services approach.

[BibT_eX]

[DOI]

João Daniel Togni

Maria Lúcia Blanck Lisbôa

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A new approach to the use of satisfiability in false path detection.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic.

[BibT_eX]

[DOI]

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

2003

Unified Theory to Build Cell-Level Transistor Networks from BDDs.

[BibT_eX]

[DOI]

Renato E. B. Poli

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

2002

Automatic Generation of Digital Cell Libraries.

[BibT_eX]

[DOI]

João Daniel Togni

Vinícius P. Correia

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Comparing Transistor-Level Implementations of 4-Input Logic Functions.

[BibT_eX]

Vinícius P. Correia

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

2001

Concepção de Circuitos e Sistemas Integrados.

[BibT_eX]

Marcelo Lubaszewski

RITA, 2001

Integrated Circuits Design Teaching Using Professional CAD Environments.

[BibT_eX]

[DOI]