Viraphol Chaiyakul

According to our database1, Viraphol Chaiyakul authored at least 9 papers between 1991 and 2000.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2000
Embedded tutorial: essential issues for IP reuse.
Proceedings of ASP-DAC 2000, 2000

Usage-based characterization of complex functional blocks for reuse in behavioral synthesis.
Proceedings of ASP-DAC 2000, 2000

1996
Clock-driven performance optimization in interactive behavioral synthesis.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1994
Condition graphs for high-quality behavioral synthesis.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

An Algorithm for Array Variable Clustering.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
High-Level Transformations for Minimizing Syntactic Variances.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Accurate layout area and delay modeling for system level design.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Timing models for high-level synthesis.
Proceedings of the conference on European design automation, 1992

1991
Layout-Area Models for High-Level Synthesis.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991


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