Daniel Gajski

Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

FPGA-friendly code compression for horizontal microcoded custom IPs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

New Strategies for System-Level Design.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

TLM: Crossing Over From Buzz To Adoption.

[BibT_eX]

[DOI]

Francine Bacchini

Laurent Maillet-Contoz

Proceedings of the 44th Design Automation Conference, 2007

2006

Verification of System Level Model Transformations.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2006

Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths .

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Transaction Routing and its Verification by Correct Model Transformations.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

A Graph Based Algorithm for Data Path Optimization in Custom Processors.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Automatic generation of transaction level models for rapid design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Generic netlist representation for system and PE level design exploration.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Designing a custom architecture for DCT using NISC technology.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Design and implementation of transducer for ARM-TMS communication.

[BibT_eX]

[DOI]

Hansu Cho

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Structural operational semantics for supporting multi-cycle operations in RTL HDLs.

[BibT_eX]

[DOI]

Shuqing Zhao

Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

System design extreme makeover.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Software and Driver Synthesis from Transaction Level Models.

[BibT_eX]

[DOI]

Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Automatic Generation of Communication Architectures.

[BibT_eX]

[DOI]

Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Custom Processor Design Using NISC: A Case-Study on DCT algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

Defining an Enhanced RTL Semantics.

[BibT_eX]

[DOI]

Shuqing Zhao

Proceedings of the 2005 Design, 2005

Functional Validation of System Level Static Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Automatic network generation for system-on-chip communication design.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

A cycle-accurate compilation algorithm for custom pipelined datapaths.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

What will system level design be when it grows up?

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

A clustering technique to optimize hardware/software synchronization.

[BibT_eX]

[DOI]

Junyu Peng

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

System-level communication modeling for network-on-chip synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Multi-metric and multi-entity characterization of applications for early system design exploration.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A formalism for functionality preserving system level transformations.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Model validation for mapping specification behaviors to processing elements.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Were the good old days all that good?: EDA then and now.

[BibT_eX]

[DOI]

Shishpal Rawat

William H. Joyner Jr.

Proceedings of the 41th Design Automation Conference, 2004

Retargetable profiling for rapid, early system-level design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Automatic generation of equivalent architecture model from functional specification.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Embedded systems education: how to teach the required skills?

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Embedded software generation from system level design languages.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Automatic generation of bus functional models from transaction level models.

[BibT_eX]

[DOI]

Dongwan Shin

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A novel memory size model for variable-mapping in system level design.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

On deriving equivalent architecture model from system specification.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Transaction Based Design: Another Buzzword or the Solution to a Design Problem?

[BibT_eX]

[DOI]

Heinz-Josef Schlebusch

Christopher K. Lennard

Frank Ghenassia

Stuart Swan

Joachim Kunkel

Proceedings of the 2003 Design, 2003

RTOS Modeling for System Level Design.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Automatic communication refinement for system level design.

[BibT_eX]

[DOI]

Dongwan Shin

Proceedings of the 40th Design Automation Conference, 2003

RTOS scheduling in transaction level models.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Transaction level modeling: an overview.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

RTOS Modeling for System Level Design.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software for SoC, 2003

2002

An ultra-fast instruction set simulator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Automatic Model Refinement for Fast Architecture Exploration.

[BibT_eX]

[DOI]

Junyu Peng

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Seamless approach for the design of control systems for power electronics and electric drives.

[BibT_eX]

[DOI]

Slim Ben Saoud

Proceedings of the IEEE International Conference on Systems, Man and Cybernetics: Bridging the Digital Divide, Yasmine Hammamet, Tunisia, October 6-9, 2002, 2002

Optimal Message-Passing for Data Coherency in Distributed Architecture.

[BibT_eX]

[DOI]

Junyu Peng

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

System-Level Abstraction Semantics.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Modeling a new RTL semantics in C++.

[BibT_eX]

[DOI]

Shuqing Zhao

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Top-Down System Level Design Methodology Using SpecC, VCC and SystemC.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Co-design of embedded controllers for power electronics and electric systems.

[BibT_eX]

[DOI]

Slim Ben Saoud

Proceedings of the 2002 IEEE International Symposium on Intelligent Control, 2002

2001

Performance-constrained hierarchical pipelining for behaviors, loops, and operations.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2001

RTL semantics and methodology.

[BibT_eX]

[DOI]

Brian Bailey

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Introduction of system level architecture exploration using the SpecC methodology.

[BibT_eX]

[DOI]

Mike Olivarez

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

C/C++: progress or deadlock in system-level specification.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Panel: The Next HDL: If C++ is the Answer, What was the Question?

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Compiling SpecC for simulation.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

System Design - A Practical Guide with SpecC.

[BibT_eX]

[DOI]

Springer, ISBN: 978-0-7923-7387-2, 2001

2000

The Specification Language SpecC within the PARADISE Design Environment.

[BibT_eX]

Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000

One language or more?: how can we design an SoC at a system level?

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Embedded tutorial: essential issues for IP reuse.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Usage-based characterization of complex functional blocks for reuse in behavioral synthesis.

[BibT_eX]

[DOI]

Nong Fan

Proceedings of ASP-DAC 2000, 2000

Reuse and protection of intellectual property in the SpecC system.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

Partitioning and pipelining for performance-constrained hardware/software systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

Panel Statement: System-Level Design: Designers' Wish List vs. Reality.

[BibT_eX]

[DOI]

Reinaldo A. Bergamaschi

Proceedings of the 12th International Symposium on System Synthesis, 1999

Rapid Prototyping with HW/SW Codesign Tool.

[BibT_eX]

[DOI]

Dai Araki

Tadatoshi Ishii

Proceedings of the 6th Symposium on Engineering of Computer-Based Systems (ECBS '99), 1999

OpenJ: An Extensible System Level Design Language.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Soft Scheduling in High Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

IP-based Design Methodology.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

A unified formal model of ISA and FSMD.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998

SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

Specification and Design of Embedded Systems.

[BibT_eX]

[DOI]

Informationstechnik Tech. Inform., 1998

IP-Centric Methodology and Specification Language.

[BibT_eX]

Proceedings of the Distributed and Parallel Embedded Systems, 1998

Hierarchical pipelining for behaviors, loops, and operations.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

System-level exploration with SpecSyn.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

1997

Model refinement for hardware-software codesign.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1997

A Scheduling and Pipelining Algorithm for Hardware/Software Systems.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on System Synthesis, 1997

Hardware/Software Partitioning and Pipelining.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

A quantitative analysis for optimizing memory allocation.

[BibT_eX]

[DOI]

Youn-Sik Hong

Choong-Hee Cho

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

System design methodologies: aiming at the 100 h design cycle.

[BibT_eX]

[DOI]

Peter Fung

IEEE Trans. Very Large Scale Integr. Syst., 1996

Component selection for high-performance pipelines.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1996

An optimal clock period selection method based on slack minimization criteria.

[BibT_eX]

[DOI]

En-Shou Chang

ACM Trans. Design Autom. Electr. Syst., 1996

Opportunities and pitfalls in HDL-based system design.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Clock-driven performance optimization in interactive behavioral synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Rapid performance estimation for system design.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

Clock optimization for high-performance pipelined design.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

Component selection in resource shared and pipelined DSP applications.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

1995

Incremental hardware estimation during hardware/software functional partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1995

Performance evaluation for application-specific architectures.

[BibT_eX]

[DOI]

Alexandru Nicolau

IEEE Trans. Very Large Scale Integr. Syst., 1995

SpecCharts: a VHDL front-end for embedded systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Specification and Design of Embedded Hardware-Software Systems.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1995

Clustering for improved system-level functional partitioning.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Closeness metrics for system-level functional partitioning.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

A memory selection algorithm for high-performance pipelines.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

SLIF: a specification-level intermediate format for system design.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

Architectural exploration for datapaths with memory hierarchy.

[BibT_eX]

[DOI]

Nancy D. Holmes

Proceedings of the 1995 European Design and Test Conference, 1995

Software estimation using a generic-processor model.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

Interfacing Incompatible Protocols Using Interface Process Generation.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

1994

A transformation-based method for loop folding.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Introduction to High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1994

Condition graphs for high-quality behavioral synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Design exploration for high-performance pipelines.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A transformation for integrating VHDL behavioral specification with synthesis and software generation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

100-hour design cycle: a test case.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

An Algorithm for Array Variable Clustering.

[BibT_eX]

[DOI]

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Synthesis of System-Level Bus Interfaces.

[BibT_eX]

[DOI]

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

An Algorithm for Generation of Behavioral Shape Functions.

[BibT_eX]

[DOI]

Nancy D. Holmes

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

A performance evaluator for parameterized ASIC architectures.

[BibT_eX]

[DOI]

Alex Nicolau

Proceedings of the Proceedings EURO-DAC'94, 1994

A System-Design Methodology: Executable-Specification Refinement.

[BibT_eX]

[DOI]

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

A component selection algorithm for high-performance pipelines.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

Protocol Generation for Communication Channels.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

1993

Component synthesis from functional descriptions.

[BibT_eX]

[DOI]

Elke A. Rundensteiner

Lubomir Bic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Synthesis of functions and procedures in behavioral VHDL.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

Architectural tradeoffs in synthesis of pipelined controls.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

Features supporting system-level specification in HDLs.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

Top-down modeling of RISC processors in VHDL.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

High-Level Transformations for Minimizing Syntactic Variances.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Partitioning algorithms for layout synthesis from register-transfer netlists.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Layout placement for sliced architecture.

[BibT_eX]

[DOI]

Lawrence L. Larmore

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

System Specification with the SpecCharts Language.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1992

System Level Specification and Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on VLSI Design, 1992

Benchmarking and the Art of Syntesis Tool Comparison.

[BibT_eX]

Proceedings of the Synthesis for Control Dominated Circuits, 1992

An efficient multi-view design model for real-time interactive synthesis.

[BibT_eX]

[DOI]

Tedd Hadley

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Accurate layout area and delay modeling for system level design.

[BibT_eX]

[DOI]

Champaka Ramachandran

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

An effective methodology for functional pipelining.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Semantics and synthesis of signals in behavioral VHDL.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

System clock estimation based on clock slack minimization.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

Timing models for high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

Specification Partitioning for System Design.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

Functional Synthesis Using Area and Delay Optimization.

[BibT_eX]

[DOI]

Elke A. Rundensteiner

Proceedings of the 29th Design Automation Conference, 1992

Youn-Long Steve Lin

[BibT_eX]

[DOI]

Springer, ISBN: 978-1-4615-3636-9, 1992

1991

Layout-Area Models for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift Transformation.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

An Algorithm for Component Selection in Performance Optimized Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

System Specification and Synthesis with the SpecCharts Language.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Glue-logic partitioning for floorplans with a rectilinear datapath.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1991

Translating system specifications to VHDL.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1991

1990

Hypertool: A Programming Aid for Message-Passing Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1990

Chippe: a system for constraint driven behavioral synthesis.

[BibT_eX]

[DOI]

Forrest Brewer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

The Role of Learning in Logic Synthesis.

[BibT_eX]

[DOI]

James R. Kipps

Int. J. Pattern Recognit. Artif. Intell., 1990

Design Synthesis and Silicon Compilation.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1990

The Component Sythesis Algorithm: Technology Mapping for Register Transfer Descriptions.

[BibT_eX]

[DOI]

Elke A. Rundensteiner

Lubomir Bic

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

A new algorithm for transistor sizing in CMOS circuits.

[BibT_eX]

[DOI]

Nels Vander Zanden

Proceedings of the European Design Automation Conference, 1990

Silicon compilation of switched: capacitor networks.

[BibT_eX]

[DOI]

Mehrdad Negahban

Proceedings of the European Design Automation Conference, 1990

Percolation Based Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

An Intermediate Representation for Behavioral Synthesis.

[BibT_eX]

[DOI]

Tedd Hadley

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

An Intelligent Component Database for Behavioral Synthesis.

[BibT_eX]

[DOI]

Gwo-Dong Chen

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Computer-aided programming for message-passing systems: problems and solutions.

[BibT_eX]

[DOI]

Proc. IEEE, 1989

Power routing in channelless floorplan layouts.

[BibT_eX]

[DOI]

Integr., 1989

Hypertool: A Programming Aid for Multicomputers.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1989

VHDL Synthesis Using Structured Modeling.

[BibT_eX]

[DOI]

Joseph Lis

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Designer Controlled Behavioral Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

A programming aid for hypercube architectures.

[BibT_eX]

[DOI]

J. Supercomput., 1988

A technique for pull-up transistor folding.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

LES: a layout expert system.

[BibT_eX]

[DOI]

Youn-Long Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Synthesis from VHDL.

[BibT_eX]

[DOI]

Joseph Lis

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

MILO: A Microarchitecture and Logic Optimizer.

[BibT_eX]

[DOI]

Nels Vander Zanden

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Design Tools for Intelligent Silicon Compilation.

[BibT_eX]

[DOI]

Barry M. Pangrle

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A Programming Aid for Message-passing Systems.

[BibT_eX]

Proceedings of the Third SIAM Conference on Parallel Processing for Scientific Computing, 1987

Improving a PLA Area by Pull-Up Transistor Folding.

[BibT_eX]

[DOI]

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

Knowledge Based Control in Micro-Architecture Design.

[BibT_eX]

[DOI]

Forrest Brewer

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

A Heuristic for Suffix Solutions.

[BibT_eX]

[DOI]

Avinoam Bilgory

IEEE Trans. Computers, 1986

CAMP: A Programming Aide for Multiprocessors.

[BibT_eX]

Jih-Kwon Peir

Proceedings of the International Conference on Parallel Processing, 1986

Flow graph representation.

[BibT_eX]

[DOI]

Alex Orailoglu

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

An expert-system paradigm for design.

[BibT_eX]

[DOI]

Forrest Brewer

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985

Comparison of five multiprocessor systems.

[BibT_eX]

[DOI]

Jih-Kwon Peir

Parallel Comput., 1985

Essential Issues in Multiprocessor Systems.

[BibT_eX]

[DOI]

Jih-Kwon Peir

Computer, 1985

Decomposition of logic networks into silicon.

[BibT_eX]

[DOI]

Steven T. Healey

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

A Parallel Pipelined Relational Query Processor.

[BibT_eX]

[DOI]

Won Kim

David J. Kuck

ACM Trans. Database Syst., 1984

Fast Execution of Loops with IF Statements.

[BibT_eX]

[DOI]

Utpal Banerjee

IEEE Trans. Computers, 1984

A Parallel Pipelined Relational Query Processor: An Architectural Overview.

[BibT_eX]

[DOI]

Won Kim

Shinya Fushimi

Proceedings of the 11th Annual Symposium on Computer Architecture, 1984

Microprocessor synthesis.

[BibT_eX]

[DOI]

Vijay K. Raj

Barry M. Pangrle

Proceedings of the 21st Design Automation Conference, 1984

Cell compilation with constraints.

[BibT_eX]

[DOI]

Proceedings of the 21st Design Automation Conference, 1984

Silicon compilers and expert systems for VLSI.

[BibT_eX]

[DOI]