Fadi J. Kurdahi

According to our database1, Fadi J. Kurdahi authored at least 193 papers between 1984 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2005, "For contributions to design automation of digital systems and to reconfigurable computing.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2019
Efficient Tracing Methodology Using Automata Processor.
ACM Trans. Embedded Comput. Syst., 2019

Power Performance Tradeoffs Using Adaptive Bit Width Adjustments on Resistive Associative Processors.
IEEE Trans. on Circuits and Systems, 2019

Hybrid pyramid-DWT-SVD dual data hiding technique for videos ownership protection.
Multimedia Tools Appl., 2019

Error-triggered Three-Factor Learning Dynamics for Crossbar Arrays.
CoRR, 2019

Spiking Neural Networks for Inference and Learning: A Memristor-based Design Perspective.
CoRR, 2019

The Information Processing Factory: Organization, Terminology, and Definitions.
CoRR, 2019

Non-Stationary Polar Codes for Resistive Memories.
CoRR, 2019

On Resistive Memories: One Step Row Readout Technique and Sensing Circuitry.
CoRR, 2019

IBCFAP: Intra-Body Communications Five-Layers Arm Phantom Model.
IEEE Access, 2019

Feasibility Study of Plant Health Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Testing Topology Adaptive Irrigation IoT with Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

The information processing factory: a paradigm for life cycle management of dependable systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

Sensitivity of Galvanic Intra-Body Communication Channel to System Parameters.
Proceedings of the Body Area Networks. Smart IoT and Big Data for Intelligent Health Management, 2019

2018
A Two-Dimensional Associative Processor.
IEEE Trans. VLSI Syst., 2018

Guest Editorial: Special Issue on Accelerated Computing.
IEEE Trans. Multi-Scale Computing Systems, 2018

Modeling and Analysis of Passive Switching Crossbar Arrays.
IEEE Trans. on Circuits and Systems, 2018

Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS.
Proceedings of the IEEE, 2018

Power optimization techniques for associative processors.
Journal of Systems Architecture - Embedded Systems Design, 2018

A Hybrid Approximate Computing Approach for Associative In-Memory Processors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Physical Multi-Layer Phantoms for Intra-Body Communications.
IEEE Access, 2018

Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Minimal Disturbed Bits in Writing Resistive Crossbar Memories.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Low-Power Resistive Associative Processor Implementation Through the Multi-Compare.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Circuit Inspired Modeling Method for Irrigation.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Design methodologies for enabling self-awareness in autonomous systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Rapid in-memory matrix multiplication using associative processor.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Extracting the Cole-Cole Model Parameters of Tissue-mimicking Materials.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017
Microarchitecture-Level SoC Design.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Approximate Memristive In-memory Computing.
ACM Trans. Embedded Comput. Syst., 2017

Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches.
IEEE Trans. on Circuits and Systems, 2017

AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement.
IET Circuits, Devices & Systems, 2017

Low Latency Approximate Adder for Highly Correlated Input Streams.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Efficient pulsed-latch implementation for multiport register files: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017

3D mesh robust watermarking technique for ownership protection.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
A case study to develop a graduate-level degree program in embedded & cyber-physical systems.
SIGBED Review, 2016

Rectangular stable power-aware mobile projection on planar surfaces.
Proceedings of the 15th ACM SIGGRAPH Conference on Virtual-Reality Continuum and Its Applications in Industry, 2016

A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Poster Abstract: Unifying Modeling Substrate for Irrigation Cyber-Physical Systems.
Proceedings of the 7th ACM/IEEE International Conference on Cyber-Physical Systems, 2016

Process variations-aware resistive associative processor design.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Resource Aggregation for Collaborative Video from Multiple Projector enabled Mobile Devices.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016

Topaz: Mining high-level safety properties from logic simulation traces.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Auto-tuning Fault Tolerance Technique for DSP-Based Circuits in Transportation Systems.
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016

Conquering MPSoC complexity with principles of a self-aware information processing factory.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Lattice-based Boolean diagrams.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Erratum to: Chapter 4 Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016

Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016

2015
Cooperative On-Chip Temperature EstimationUsing Multiple Virtual Sensors.
Embedded Systems Letters, 2015

Thermal sensor allocation for SoCs based on temperature gradients.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

DWT-based watermarking technique for video authentication.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

NUVA: Architectural support for runtime verification of parametric specifications over multicores.
Proceedings of the 2015 International Conference on Compilers, 2015

Intra-body communication model based on variable biological parameters.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Multicopy Cache: A Highly Energy-Efficient Cache Architecture.
ACM Trans. Embedded Comput. Syst., 2014

Mobile Collaborative Video.
IEEE Trans. Circuits Syst. Video Techn., 2014

Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems.
IEEE Trans. on Circuits and Systems, 2014

Joint Power Management and Adaptive Modulation and Coding for Wireless Communications Systems With Unreliable Buffering Memories.
IEEE Trans. on Circuits and Systems, 2014

Equi-Noise: A Statistical Model That Combines Embedded Memory Failures and Channel Noise.
IEEE Trans. on Circuits and Systems, 2014

Low power reduced-complexity error-resilient MIMO detector.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

State dependent statistical timing model for voltage scaled circuits.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Vision-inspired global routing for enhanced performance and reliability.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Architectural support for runtime verification on ccNUMA multiprocessors.
Proceedings of the 8th International Design and Test Symposium, 2013

Low overhead correction scheme for unreliable LDPC buffering.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

Heterogeneous memory management for 3D-DRAM and external DRAM with QoS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Error-aware power management for memory dominated OFDM systems.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling.
IEEE Trans. VLSI Syst., 2012

Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications.
ACM Trans. Embedded Comput. Syst., 2012

Parity-based mono-Copy Cache for low power consumption and high reliability.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Collaborative video playback on a federation of tiled mobile projectors enabled by visual feedback.
Proceedings of the Third Annual ACM SIGMM Conference on Multimedia Systems, 2012

History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Fast error aware model for arithmetic and logic circuits.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Error resilient MIMO detector for memory-dominated wireless communication systems.
Proceedings of the 2012 IEEE Global Communications Conference, 2012

Reliable low power Distributed Arithmetic filters via N-Modular Redundancy.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation.
IEEE Trans. VLSI Syst., 2011

A Multi-Granularity Power Modeling Methodology for Embedded Processors.
IEEE Trans. VLSI Syst., 2011

Embedded Memories Fault-Tolerant Pre- and Post-Silicon Optimization.
IEEE Trans. VLSI Syst., 2011

On leakage power optimization in clock tree networks for ASICs and general-purpose processors.
SUSCOM, 2011

Reconfigurable filter implementation of a matched-filter based spectrum sensor for Cognitive Radio systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Adjustable supply voltages and refresh cycle for process variations, temperature changes, and device degradation adaptation in 1T1C embedded DRAM.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Area, reconfiguration delay and reliability trade-offs in designing reliable multi-mode FIR filters.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

A Class of Low Power Error Compensation Iterative Decoders.
Proceedings of the Global Communications Conference, 2011

Camera-based video synchronization for a federation of mobile projectors.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2011

Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010
CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis.
IEEE Trans. VLSI Syst., 2010

Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications.
IEEE Trans. VLSI Syst., 2010

Low-Power Multimedia System Design by Aggressive Voltage Scaling.
IEEE Trans. VLSI Syst., 2010

Designing working systems with imperfect chips.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Effect of body biasing on embedded SRAM failure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Placement-aware partial reconfiguration for a class of FIR-like structures.
Proceedings of the 17th International Conference on Telecommunications, 2010

RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

A Unified Hardware and Channel Noise Model for Communication Systems.
Proceedings of the Global Communications Conference, 2010

Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Process variation aware transcoding for low power H.264 decoding.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.
Proceedings of the 7th Conference on Computing Frontiers, 2010

E < MC2: less energy through multi-copy cache.
Proceedings of the 2010 International Conference on Compilers, 2010

2009
A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment.
IEEE Trans. VLSI Syst., 2009

System-level PVT variation-aware power exploration of on-chip communication architectures.
ACM Trans. Design Autom. Electr. Syst., 2009

Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems.
Proceedings of the FCCM 2009, 2009

Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling.
Proceedings of the Design, Automation and Test in Europe, 2009

TRAM: A tool for Temperature and Reliability Aware Memory Design.
Proceedings of the Design, Automation and Test in Europe, 2009

A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).
Proceedings of the 2009 International Conference on Compilers, 2009

Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Cross-layer co-exploration of exploiting error resilience for video over wireless applications.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

Methodology for multi-granularity embedded processor power model generation for an ESL design flow.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

A partial memory protection scheme for higher effective yield of embedded memory for video data.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

2007
A scalable embedded JPEG 2000 architecture.
Journal of Systems Architecture, 2007

A hierarchical pipelining architecture and FPGA implementation for lifting-based 2-D DWT.
J. Real-Time Image Processing, 2007

Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications.
International Journal of Parallel Programming, 2007

Fault Tolerant Approaches Targeting Ultra Low Power Communications System Design.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Cross Layer Error Exploitation for Aggressive Voltage Scaling.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

System level power estimation methodology with H.264 decoder prediction IP case study.
Proceedings of the 25th International Conference on Computer Design, 2007

Limits on voltage scaling for caches utilizing fault tolerant techniques.
Proceedings of the 25th International Conference on Computer Design, 2007

Power Management for Cognitive Radio Platforms.
Proceedings of the Global Communications Conference, 2007

Error-Aware Design.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

LEAF: A System Level Leakage-Aware Floorplanner for SoCs.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
Compile-time area estimation for LUT-based FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2006

System-Level SRAM Yield Enhancement.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

System-level power-performance trade-offs in bus matrix communication architecture synthesis.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Floorplan driven leakage power aware IP-based SoC design space exploration.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
A Scalable Embedded JPEG2000 Architecture.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Reconfigurable computing: is it ready for industry.
Proceedings of the International Conference on Pervasive Services 2005, 2005

Improving effective yield through error tolerant system design.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

On combining iteration space tiling with data space tiling for scratch-pad memory systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A high-performance parallel mode EBCOT encoder architecture design for JPEG2000.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

2003
Automatic compilation to a coarse-grained reconfigurable system-opn-chip.
ACM Trans. Embedded Comput. Syst., 2003

A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Guest editorial special issue on system synthesis.
IEEE Trans. VLSI Syst., 2002

Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note).
Proceedings of the Euro-Par 2002, 2002

A Complete Data Scheduler for Multi-Context Reconfigurable Architectures.
Proceedings of the 2002 Design, 2002

2001
A framework for reconfigurable computing: task scheduling and context management.
IEEE Trans. VLSI Syst., 2001

Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing.
Journal of Systems Architecture, 2001

A data scheduler for multi-context reconfigurable architectures.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems.
Proceedings of the 38th Design Automation Conference, 2001

A constraint-based application model and scheduling techniques for power-aware systems.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
Design and Implementation of the MorphoSys Reconfigurable Computing Processor.
VLSI Signal Processing, 2000

MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications.
IEEE Trans. Computers, 2000

Guest Editors' Introduction: Configurable Computing.
IEEE Design & Test of Computers, 2000

Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

MorphoSys: case study of a reconfigurable computing system targeting multimedia applications.
Proceedings of the 37th Conference on Design Automation, 2000

1999
System-level Time-stationary Control Synthesis for Pipelined Data Paths.
VLSI Design, 1999

Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs.
IEEE Trans. VLSI Syst., 1999

High-level synthesis of recoverable VLSI microarchitectures.
IEEE Trans. VLSI Syst., 1999

MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application.
Proceedings of the Parallel and Distributed Processing, 1999

The MorphoSys Parallel Reconfigurable System.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

The MorphoSys Dynamically Reconfigurable System-on-Chip.
Proceedings of the 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), 1999

Kernel Scheduling in Reconfigurable Computing.
Proceedings of the 1999 Design, 1999

1998
On the Characterization of Multi-Point Nets in Electronic Designs.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Layout-Driven High Level Synthesis for FPGA Based Architectures.
Proceedings of the 1998 Design, 1998

1997
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators.
ACM Trans. Design Autom. Electr. Syst., 1997

A unified lower bound estimation technique for high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Optimal algorithms for recovery point insertion in recoverable microarchitectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

RTL synthesis with physical and controller information.
Proceedings of the European Design and Test Conference, 1997

ChipEst-FPGA: a tool for chip level area and timing estimation of lookup table based FPGAs for high level applications.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Behavioral Modeling of an ATM Switch using SpecCharts.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Layout-Driven RTL Binding Techniques for High-Level Synthesis.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Area and Timing Estimation for Lookup Table Based FPGAs.
Proceedings of the 1996 European Design and Test Conference, 1996

High-Level Synthesis of Recoverable Microarchitectures.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
An Optimal Scheduling Approach Using Lower Bound in High-Level Synthesis.
IEICE Transactions, 1995

A comprehensive estimation technique for high-level synthesis.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures.
Proceedings of the Digest of Papers: FTCS-25, 1995

1994
Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

On the intrinsic Rent parameter and spectra-based partitioning methodologies.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

An Empirical Study on the Effects of Physical Design in High-Level Synthesis.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Controller and datapath trade-offs in hierarchical RT-level synthesis.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Comprehensive lower bound estimation from behavioral descriptions.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A performance driven logic synthesis system using delay estimator.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Incorporating the Controller Effects During Register Transfer Level Synthesis.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Hierarchical design space exploration for a class of digital systems.
IEEE Trans. VLSI Syst., 1993

Evaluating layout area tradeoffs for high level applications.
IEEE Trans. VLSI Syst., 1993

On clustering for maximal regularity extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

A logic synthesis system based on global dynamic extraction and flexible cost.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

1992
Accurate layout area and delay modeling for system level design.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Partitioning by Regularity Extraction.
Proceedings of the 29th Design Automation Conference, 1992

1991
Automatic Synthesis of Time-Stationary Controllers for Pipelined Data Paths.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

LAST: a Layout Area and Shape function esTimator for high level applications.
Proceedings of the conference on European design automation, 1991

1989
Techniques for area estimation of VLSI layouts.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1987
REAL: a program for REgister ALlocation.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
PLEST: a program for area estimation of VLSI integrated circuits.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1984
A general methodology for synthesis and verification of register-transfer designs.
Proceedings of the 21st Design Automation Conference, 1984


  Loading...