Fadi J. Kurdahi
Orcid: 0000-0002-6982-365X
According to our database1,
Fadi J. Kurdahi
authored at least 234 papers
between 1984 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2005, "For contributions to design automation of digital systems and to reconfigurable computing.".
Timeline
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Online presence:
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on orcid.org
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Bibliography
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023
Offline Training-Based Mitigation of IR Drop for ReRAM-Based Deep Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
An Accurate Non-accelerometer-based PPG Motion Artifact Removal Technique using CycleGAN.
ACM Trans. Comput. Heal., January, 2023
IEEE Trans. Emerg. Top. Comput., 2023
Inf., 2023
AudioFool: Fast, Universal and synchronization-free Cross-Domain Attack on Speech Recognition.
CoRR, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Information Processing Factory 2.0 - Self-awareness for Autonomous Collaborative Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
IEEE Trans. Knowl. Data Eng., 2022
The Self-Aware Information Processing Factory Paradigm for Mixed-Critical Multiprocessing.
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Guest Editorial: Secure Radio-Frequency (RF)-Analog Electronics and Electromagnetics.
ACM J. Emerg. Technol. Comput. Syst., 2022
Accurate Prediction of ReRAM Crossbar Performance Under I-V Nonlinearity and IR Drop.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Embed. Syst. Lett., 2021
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Cost- and Dataset-free Stuck-at Fault Mitigation for ReRAM-based Deep Learning Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
NEWERTRACK: ML-Based Accurate Tracking of In-Mouth Nutrient Sensors Position Using Spectrum-Wide Information.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Biometric Identity Based on Intra-Body Communication Channel Characteristics and Machine Learning.
Sensors, 2020
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
IEEE Des. Test, 2020
IEEE Access, 2020
R2AD: Randomization and Reconstructor-based Adversarial Defense on Deep Neural Network.
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Learning to Predict IR Drop with Effective Training for ReRAM-based Neural Network Hardware.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
ACM Trans. Embed. Comput. Syst., 2019
Power Performance Tradeoffs Using Adaptive Bit Width Adjustments on Resistive Associative Processors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Multim. Tools Appl., 2019
Spiking Neural Networks for Inference and Learning: A Memristor-based Design Perspective.
CoRR, 2019
CoRR, 2019
CoRR, 2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
RRAM Endurance and Retention: Challenges, Opportunities and Implications on Reliable Design.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 2019 IEEE Global Communications Conference, 2019
The information processing factory: a paradigm for life cycle management of dependable systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019
Proceedings of the Body Area Networks. Smart IoT and Big Data for Intelligent Health Management, 2019
Effect of Asymmetric Nonlinearity Dynamics in RRAMs on Spiking Neural Network Performance.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Proc. IEEE, 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Computational and Communication Reduction Technique in Machine Learning Based Near Sensor Applications.
Proceedings of the 30th International Conference on Microelectronics, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement.
IET Circuits Devices Syst., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Efficient pulsed-latch implementation for multiport register files: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
A case study to develop a graduate-level degree program in embedded & cyber-physical systems.
SIGBED Rev., 2016
Proceedings of the 15th ACM SIGGRAPH Conference on Virtual-Reality Continuum and Its Applications in Industry, 2016
A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 7th ACM/IEEE International Conference on Cyber-Physical Systems, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Resource Aggregation for Collaborative Video from Multiple Projector enabled Mobile Devices.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Auto-tuning Fault Tolerance Technique for DSP-Based Circuits in Transportation Systems.
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016
Conquering MPSoC complexity with principles of a self-aware information processing factory.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Erratum to: Chapter 4 Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016
Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016
2015
IEEE Embed. Syst. Lett., 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
NUVA: Architectural support for runtime verification of parametric specifications over multicores.
Proceedings of the 2015 International Conference on Compilers, 2015
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
ACM Trans. Embed. Comput. Syst., 2014
Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Joint Power Management and Adaptive Modulation and Coding for Wireless Communications Systems With Unreliable Buffering Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Equi-Noise: A Statistical Model That Combines Embedded Memory Failures and Channel Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip.
Microprocess. Microsystems, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications.
ACM Trans. Embed. Comput. Syst., 2012
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012
Collaborative video playback on a federation of tiled mobile projectors enabled by visual feedback.
Proceedings of the Third Annual ACM SIGMM Conference on Multimedia Systems, 2012
History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 2012 IEEE Global Communications Conference, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
2011
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
On leakage power optimization in clock tree networks for ASICs and general-purpose processors.
Sustain. Comput. Informatics Syst., 2011
Reconfigurable filter implementation of a matched-filter based spectrum sensor for Cognitive Radio systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Adjustable supply voltages and refresh cycle for process variations, temperature changes, and device degradation adaptation in 1T1C embedded DRAM.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Area, reconfiguration delay and reliability trade-offs in designing reliable multi-mode FIR filters.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Proceedings of the Global Communications Conference, 2011
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2011
Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
2010
CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 17th International Conference on Telecommunications, 2010
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010
Proceedings of the Global Communications Conference, 2010
Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.
Proceedings of the 7th Conference on Computing Frontiers, 2010
Proceedings of the 2010 International Conference on Compilers, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
System-level PVT variation-aware power exploration of on-chip communication architectures.
ACM Trans. Design Autom. Electr. Syst., 2009
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems.
Proceedings of the FCCM 2009, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).
Proceedings of the 2009 International Conference on Compilers, 2009
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008
System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Cross-layer co-exploration of exploiting error resilience for video over wireless applications.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
Methodology for multi-granularity embedded processor power model generation for an ESL design flow.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
A partial memory protection scheme for higher effective yield of embedded memory for video data.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008
2007
A hierarchical pipelining architecture and FPGA implementation for lifting-based 2-D DWT.
J. Real Time Image Process., 2007
Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications.
Int. J. Parallel Program., 2007
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
System level power estimation methodology with H.264 decoder prediction IP case study.
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the Global Communications Conference, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the 4th IEEE Consumer Communications and Networking Conference, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories.
Proceedings of the Advances in Computer Systems Architecture, 2007
2006
ACM Trans. Design Autom. Electr. Syst., 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
System-level power-performance trade-offs in bus matrix communication architecture synthesis.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006
2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
Proceedings of the International Conference on Pervasive Services 2005, 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
On combining iteration space tiling with data space tiling for scratch-pad memory systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
2003
ACM Trans. Embed. Comput. Syst., 2003
A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002
MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note).
Proceedings of the Euro-Par 2002, 2002
Proceedings of the 2002 Design, 2002
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing.
J. Syst. Archit., 2001
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems.
Proceedings of the 38th Design Automation Conference, 2001
A constraint-based application model and scheduling techniques for power-aware systems.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture.
Proceedings of the 2001 International Conference on Compilers, 2001
2000
J. VLSI Signal Process., 2000
<i>MorphoSys</i>: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications.
IEEE Trans. Computers, 2000
Guest Editors' Introduction: Configurable Computing.
IEEE Des. Test Comput., 2000
Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization.
Proceedings of the 13th International Symposium on System Synthesis, 2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications.
Proceedings of the 37th Conference on Design Automation, 2000
1999
VLSI Design, 1999
Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application.
Proceedings of the Parallel and Distributed Processing, 1999
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999
Proceedings of the 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), 1999
1998
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
Proceedings of the 1998 Design, 1998
1997
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators.
ACM Trans. Design Autom. Electr. Syst., 1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the European Design and Test Conference, 1997
ChipEst-FPGA: a tool for chip level area and timing estimation of lookup table based FPGAs for high level applications.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Proceedings of the 9th International Symposium on System Synthesis, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
1995
IEICE Trans. Inf. Syst., 1995
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995
Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures.
Proceedings of the Digest of Papers: FTCS-25, 1995
1994
Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Proceedings of the Seventh International Conference on VLSI Design, 1994
Proceedings of the 7th International Symposium on High Level Synthesis, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
IEEE Trans. Very Large Scale Integr. Syst., 1993
IEEE Trans. Very Large Scale Integr. Syst., 1993
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993
1992
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991
Proceedings of the conference on European design automation, 1991
1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989
1987
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987
1986
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986
1984
Proceedings of the 21st Design Automation Conference, 1984