Vishal Saxena

Orcid: 0000-0002-5080-917X

According to our database1, Vishal Saxena authored at least 45 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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On csauthors.net:

Bibliography

2024
Optical Interconnects Using Hybrid Integration of CMOS and Silicon-Photonic ICs.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2023
Compact Modeling and Rapid Simulation of Silicon Photonic Micro-Disk and Ring Modulators.
CoRR, 2023

Automatic In-situ Optical Linearization of Silicon Photonic Ring-Assisted MZ Modulator for Integrated RF Photonic SoCs.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

A Silicon Photonic Reconfigurable Optical Analog Processor (SiROAP) with a 4x4 Optical Mesh.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Power Linear DACs (PLDACs) for Configuration and Control of Silicon Photonic Integrated Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
A Deep Unsupervised Feature Learning Spiking Neural Network With Binarized Classification Layers for the EMNIST Classification.
IEEE Trans. Emerg. Top. Comput. Intell., 2022

A Hybrid CMOS Photonic 25Gbps Microring Transmitter with a -0.5-1.2V Direct-Coupled Drive.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Hybrid CMOS-RRAM Spiking CNNs with Time-Domain Max-pooling and Integrator Re-use.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Mixed-Signal Neuromorphic Computing Circuits Using Hybrid CMOS-RRAM Integration.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Analysis of Trade-offs in RF Photonic Links based on Multi-Bias Tuning of Silicon Photonic Ring-Assisted Mach Zehnder Modulators.
CoRR, 2021

A Mixed-Signal Convolutional Neural Network Using Hybrid CMOS-RRAM Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Rapid Simulation of Photonic Integrated Circuits Using Verilog-A Compact Models.
IEEE Trans. Circuits Syst., 2020

Analysis of RF Photonic Link using Silicon Photonic Ring-Assisted Mach Zehnder Modulator.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Process-Variation Robust RRAM-Compatible CMOS Neuron for Neuromorphic System-on-a-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Continuous Learning in a Single-Incremental-Task Scenario with Spike Features.
Proceedings of the International Conference on Neuromorphic Systems, 2020

2019
Deep Convolutional Spiking Neural Networks for Image Classification.
CoRR, 2019

A CMOS Photonic Optical PAM4 Transmitter Linearized using Three-Segment Ring Modulator.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

High LRS-Resistance CMOS Memristive Synapses for Energy-Efficient Neuromorphic SoCs.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Feature Extraction using Spiking Convolutional Neural Networks.
Proceedings of the International Conference on Neuromorphic Systems, 2019

2018
From Design to Test: A High-Speed PRBS.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Dendritic-Inspired Processing Enables Bio-Plausible STDP in Compound Binary Synapses.
CoRR, 2018

Design and Compact Modeling of Silicon-Photonic Coupling-Based Ring Modulators for Optical Interconnects.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Design and Modeling of Silicon Photonic Ring-Based Linearized RF-to-Optical Modulator.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A Compact CMOS Memristor Emulator Circuit and its Applications.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 3D-Integrated 56 Gb/s NRZ/PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter.
Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018

2017
Case Study of a Hybrid Optoelectronic Limiting Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Towards spiking neuromorphic system-on-a-chip with bio-plausible synapses using emerging devices.
Proceedings of the 4th ACM International Conference on Nanoscale Computing and Communication, 2017

Behavioral modeling and characterization of silicon photonic Mach-Zehnder modulator.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Realization of a 10 GHz PLL in IBM 130 nm SiGe BiCMOS process for optical transmitter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Enabling bio-plausible multi-level STDP using CMOS neurons with dendrites and bistable RRAMs.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

2016
Modeling and optimization of the bond-wire interface in a Hybrid CMOS-photonic traveling-wave MZM transmitter.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Tutorial 4B: ADC design - from system architecture to transistor level design.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015
Design Considerations for Traveling-Wave Modulator-Based CMOS Photonic Transmitters.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

A comprehensive design approach for a MZM based PAM-4 silicon photonic transmitter.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A CMOS spiking neuron for dense memristor-synapse connectivity for brain-inspired computing.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

2014
Compact Verilog-A modeling of silicon traveling-wave modulator for hybrid CMOS photonic circuit design.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
Design of a 10-Gb/s integrated limiting receiver for silicon photonics interconnects.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Systematic synthesis of cascaded continuous-time ΔΣ ADCs for wideband data conversion.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012
A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-ΔΣ ADC with 1.5 cycle quantizer delay and improved STF.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Design of wideband continuous-time ΔΣ ADCs using two-step quantizers.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011
Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2005
A Non-invasive, Multi-modality Approach Based on NIRS and MRI Techniques For Monitoring Intracranial Brain Tumor Angiogenesis.
Proceedings of the 34th Applied Image Pattern Recognition Workshop (AIPR 2005), 2005


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