Kadaba Lakshmikumar

Orcid: 0000-0001-7621-4177

According to our database1, Kadaba Lakshmikumar authored at least 17 papers between 1996 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Awards

IEEE Fellow

IEEE Fellow 2013, "For contributions to design of mixed signal CMOS integrated circuits for telecommunications".

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Optical Interconnects Using Hybrid Integration of CMOS and Silicon-Photonic ICs.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2023
A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
An Interference Suppression Technique for Millimeter-Wave LC VCOs Using a Multiport Coupled Inductor.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

High-Performance CMOS TIA for Data Center Optical Interconnects.
Proceedings of the 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2022

2021
A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling.
IEEE J. Solid State Circuits, 2021

2019
A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links.
IEEE J. Solid State Circuits, 2019

2018
A process and temperature insensitive CMOS linear TIA for 100 Gbps/λ PAM-4 optical links.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2016
Patent Abstracts.
IEEE J. Solid State Circuits, 2016

2009
Analog PLL Design With Ring Oscillators at Low-Gigahertz Frequencies in Nanometer CMOS: Challenges and Solutions.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 3-level PWM ADSL2+ CO line driver.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2007
A Process and Temperature Compensated Two-Stage Ring Oscillator.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2003
A low-power 0.13μm CMOS OC-48 SONET and XAUI compliant SERDES.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

A fully-integrated 10.5 to 13.5 Gbps transceiver in 0.13 μm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2001
High-speed serial transceivers for data communication systems.
IEEE Commun. Mag., 2001

2000
A CMOS self-calibrating frequency synthesizer.
IEEE J. Solid State Circuits, 2000

1999
A low-voltage line driver for digital signaling interface.
IEEE J. Solid State Circuits, 1999

1996
A baseband processor for IS-54 cellular telephony.
IEEE J. Solid State Circuits, 1996


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