Vishnu Ravinuthula

According to our database, Vishnu Ravinuthula authored at least 4 papers between 2004 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz.

Vishnu Ravinuthula, William Bright, Mark Weaver, Kenneth Maclean, Scott Kaylor, Sidharth Balasubramanian, Jesse Coulon, Robert Keller, Bao Nguyen, Ebenezer Dwobeng

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2011

Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver.

Andrew K. Joy, Hugh Mair, Hae-Chang Lee, Arnold Feldman, Clemenz L. Portmann, Neil Bulman, Eugenia Cordero Crespo, Peter Hearne, Patty Huang, Ben Kerr, Pulkit Khandelwal, Franz Kuhlmann, Shaun Lytollis, Joaquim Machado, Casey Morrison, Scott Morrison, Shahriar Rabii, Dushmantha Rajapaksha, Vishnu Ravinuthula, Giuseppe Surace

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

Time-mode circuits for analog computation.

Vishnu Ravinuthula, Vaibhav Garg, John G. Harris, José A. B. Fortes

Int. J. Circuit Theory Appl., 2009

2004

Time-based arithmetic using step functions.

Vishnu Ravinuthula, John G. Harris

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004