Giuseppe Surace

According to our database1, Giuseppe Surace authored at least 6 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET.
IEEE J. Solid State Circuits, 2020


2019

2016
10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2011
Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011


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