Pulkit Khandelwal

According to our database1, Pulkit Khandelwal authored at least 15 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Surface-based parcellation and vertex-wise analysis of ultra high-resolution ex vivo 7 tesla MRI in neurodegenerative diseases.
CoRR, 2024

2023
Deep label fusion: A generalizable hybrid multi-atlas and deep convolutional neural network for medical image segmentation.
Medical Image Anal., 2023

Automated deep learning segmentation of high-resolution 7 T ex vivo MRI for quantitative analysis of structure-pathology correlations in neurodegenerative diseases.
CoRR, 2023

Image-to-Image Translation Between Tau Pathology and Neuronal Metabolism PET in Alzheimer Disease with Multi-domain Contrastive Learning.
Proceedings of the Machine Learning in Clinical Neuroimaging - 6th International Workshop, 2023


2022
Fully Automated 3D Segmentation and Diffeomorphic Medial Modeling of the Left Ventricle Mitral Valve Complex in Ischemic Mitral Regurgitation.
Medical Image Anal., 2022

2021
Spine and Individual Vertebrae Segmentation in Computed Tomography Images Using Geometric Flows and Shape Priors.
Frontiers Comput. Sci., 2021

Gray Matter Segmentation in Ultra High Resolution 7 Tesla ex vivo T2w MRI of Human Brain Hemispheres.
CoRR, 2021

2020
Benchmarking Human Performance in Semi-Automated Image Segmentation.
Interact. Comput., 2020

Domain Generalizer: A Few-Shot Meta Learning Framework for Domain Generalization in Medical Imaging.
Proceedings of the Domain Adaptation and Representation Transfer, and Distributed and Collaborative Learning, 2020

2017
A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Link performance investigation of industry first 100G PAM4 IC chipset with real-time DSP for data center connectivity.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016


2011
Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2007
A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


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