Viveka Konandur Rajanna
Orcid: 0000-0001-5353-7109
According to our database1,
Viveka Konandur Rajanna authored at least 17 papers
between 2016 and 2026.
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Bibliography
2026
SRAM Static Entropy Extraction From Every Single Transistor in Unmodified Bitcell and Data Fingerprinting for Provenance Assurance.
IEEE J. Solid State Circuits, February, 2026
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2024
122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
SRAM Physically Unclonable Function Extracting Static Entropy from Every Bitcell Transistor for 6 bit/bitcell and Data Fingerprinting Capability for Provenance Assurance.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
IEEE J. Solid State Circuits, 2022
Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications.
IEEE J. Solid State Circuits, 2021
Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm<sup>2</sup> per Receptor for Scaling to Human-Like Tactile Sensing Density.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm<sup>2</sup> and 749-1, 459 TOPS/W in 28nm.
Proceedings of the 47th ESSCIRC 2021, 2021
2019
Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2016
A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2016