Wan-Luan Lee

According to our database, Wan-Luan Lee authored at least 7 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Scalable Code Generation for RTL Simulation of Deep Learning Accelerators With MLIR.

Jie Tong, Wan-Luan Lee, Umit Yusuf Ogras, Tsung-Wei Huang

Proceedings of the Euro-Par 2025: Parallel Processing, 2025

SimPart: A Simple Yet Effective Replication-Aided Partitioning Algorithm for Logic Simulation on GPU.

Yi-Hua Chung, Shui Jiang, Wan-Luan Lee, Yanqing Zhang, Haoxing Ren, Tsung-Yi Ho, Tsung-Wei Huang

Proceedings of the Euro-Par 2025: Parallel Processing, 2025

iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis.

Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner.

Wan-Luan Lee, Dian-Lun Lin, Cheng-Hsiang Chiu, Ulf Schlichtmann, Tsung-Wei Huang

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

PathGen: An Efficient Parallel Critical Path Generation Algorithm.

Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

G-PASTA: GPU-Accelerated Partitioning Algorithm for Static Timing Analysis.

Boyang Zhang, Dian-Lun Lin, Che Chang, Cheng-Hsiang Chiu, Bojue Wang, Wan-Luan Lee, Chih-Chun Chang, Donghao Fang, Tsung-Wei Huang

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner.

Wan-Luan Lee, Dian-Lun Lin, Tsung-Wei Huang, Shui Jiang, Tsung-Yi Ho, Yibo Lin, Bei Yu

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024