Wei-Shen Wang

According to our database, Wei-Shen Wang authored at least 9 papers between 2004 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2009

Statistical analysis of circuit timing using majorization.

Michael Orshansky, Wei-Shen Wang

Commun. ACM, 2009

2007

Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters.

Wei-Shen Wang, Michael Orshansky

J. Low Power Electron., 2007

2006

Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation.

Wei-Shen Wang, Michael Orshansky

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation.

Wei-Shen Wang, Michael Liu, Michael Orshansky

J. Low Power Electron., 2006

Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips.

Michael Orshansky, Wei-Shen Wang, Martine Ceberio, Gang Xiang

Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006

FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs.

Bin Zhang, Wei-Shen Wang, Michael Orshansky

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Robust estimation of parametric yield under limited descriptions of uncertainty.

Wei-Shen Wang, Michael Orshansky

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty.

Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky

Proceedings of the 43rd Design Automation Conference, 2006

2004

Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation.

Michael Liu, Wei-Shen Wang, Michael Orshansky

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004