Michael Orshansky

ACM Trans. Embed. Comput. Syst., January, 2024

2023

A Provably Secure Strong PUF Based on LWE: Construction and Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, February, 2023

Artemis: HE-Aware Training for Efficient Privacy-Preserving Machine Learning.

[BibT_eX]

[DOI]

Yeonsoo Jeon

Mattan Erez

CoRR, 2023

Enhancing Cross-Category Learning in Recommendation Systems with Multi-Layer Embedding Training.

[BibT_eX]

[DOI]

Zihao Deng

Benjamin Ghaemmaghami

CoRR, 2023

Mixed-Precision Quantization with Cross-Layer Dependencies.

[BibT_eX]

[DOI]

CoRR, 2023

A Provably Secure Strong PUF based on LWE: Construction and Implementation.

[BibT_eX]

[DOI]

CoRR, 2023

2022

Power-based Attacks on Spatial DNN Accelerators.

[BibT_eX]

[DOI]

Ge Li

Mohit Tiwari

ACM J. Emerg. Technol. Comput. Syst., 2022

High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks.

[BibT_eX]

[DOI]

Aditya Thimmaiah

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM.

[BibT_eX]

[DOI]

Zihao Deng

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2021

Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks.

[BibT_eX]

[DOI]

Meizhi Wang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020

A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Training with Multi-Layer Embeddings for Model Reduction.

[BibT_eX]

[DOI]

Benjamin Ghaemmaghami

CoRR, 2020

Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks.

[BibT_eX]

[DOI]

Xiaodan Xi

Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

2019

Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow.

[BibT_eX]

[DOI]

Ge Li

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

2018

Fresh re-keying with strong PUFs: A new approach to side-channel security.

[BibT_eX]

[DOI]

Xiaodan Xi

Aydin Aysu

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Horizontal side-channel vulnerabilities of post-quantum key exchange protocols.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Efficient helper data reduction in SRAM PUFs via lossy compression.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Binary Ring-LWE hardware with power side-channel countermeasures.

[BibT_eX]

[DOI]

Aydin Aysu

Mohit Tiwari

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Efficient simulation of EM side-channel attack resilience.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A new maskless debiasing method for lightweight physical unclonable functions.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

2016

Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Exploiting randomness in sketching for efficient hardware implementation of machine learning applications.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Multiple Attempt Write Strategy for Low Energy STT-RAM.

[BibT_eX]

[DOI]

Jaeyoung Park

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

PolyGP: Improving GP-based analog optimization through accurate high-order monomials and semidefinite relaxation.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A Monte Carlo simulation flow for SEU analysis of sequential circuits.

[BibT_eX]

[DOI]

Meng Li

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Novel power grid reduction method based on L1 regularization.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Multi-level approximate logic synthesis under general error constraints.

[BibT_eX]

[DOI]

Jin Miao

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2013

Probabilistic strain optimization under constraint uncertainty.

[BibT_eX]

[DOI]

BMC Syst. Biol., 2013

Low-energy digital filter design based on controlled timing error acceptance.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Approximate logic synthesis under general error magnitude and frequency constraints.

[BibT_eX]

[DOI]

Jin Miao

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Novel strong PUF based on nonlinearity of MOSFET subthreshold operation.

[BibT_eX]

[DOI]

Mukund Kalyanaraman

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Approximate computing: An emerging paradigm for energy-efficient design.

[BibT_eX]

[DOI]

Jie Han

Proceedings of the 18th IEEE European Test Symposium, 2013

Gene modification identification under flux capacity uncertainty.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics.

[BibT_eX]

[DOI]

Kareem Ragab

Mario Lok

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

An accurate sparse-matrix based framework for statistical static timing analysis.

[BibT_eX]

[DOI]

Integr., 2012

Highly Secure Strong PUF based on Nonlinearity of MOSFET Subthreshold Operation.

[BibT_eX]

[DOI]

Mukund Kalyanaraman

IACR Cryptol. ePrint Arch., 2012

Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation.

[BibT_eX]

[DOI]

Kareem Ragab

Ranjit Gharpurey

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Low-energy signal processing using circuit-level timing-error acceptance.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Modeling and synthesis of quality-energy optimal approximate adders.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

Coupling timing objectives with optical proximity correction for improved timing yield.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Controlled timing-error acceptance for low energy IDCT design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime.

[BibT_eX]

[DOI]

Mehmet Basoglu

Mattan Erez

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

An algorithm for exploiting modeling error statistics to enable robust analog optimization.

[BibT_eX]

[DOI]

Mario Lok

Kareem Ragab

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

SMATO: Simultaneous mask and target optimization for improving lithographic process window.

[BibT_eX]

[DOI]

Shayak Banerjee

Kanak B. Agarwal

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A methodology for propagating design tolerances to shape tolerances for use in manufacturing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects.

[BibT_eX]

[DOI]

Shayak Banerjee

Kanak B. Agarwal

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

Statistical analysis of circuit timing using majorization.

[BibT_eX]

[DOI]

Commun. ACM, 2009

Mitigation of intra-array SRAM variability using adaptive voltage architecture.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

The Search for Alternative Computational Paradigms.

[BibT_eX]

[DOI]

Jaijeet S. Roychowdhury

Douglas L. Jones

Jan M. Rabaey

IEEE Des. Test Comput., 2008

Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation.

[BibT_eX]

[DOI]

Bin Zhang

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Electrically driven optical proximity correction based on linear programming.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Design for Manufacturability and Statistical Design - A Constructive Approach.

[BibT_eX]

[DOI]

Sani R. Nassif

Duane S. Boning

Series on integrated circuits and systems, Springer, ISBN: 978-0-387-30928-6, 2008

2007

A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Architecting a reliable CMP switch architecture.

[BibT_eX]

[DOI]

Kypros Constantinides

ACM Trans. Archit. Code Optim., 2007

Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters.

[BibT_eX]

[DOI]

J. Low Power Electron., 2007

Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies

[BibT_eX]

[DOI]

CoRR, 2007

A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Estimating path delay distribution considering coupling noise.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation.

[BibT_eX]

[DOI]

Michael Liu

J. Low Power Electron., 2006

Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips.

[BibT_eX]

[DOI]

Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006

FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs.

[BibT_eX]

[DOI]

Bin Zhang

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Tutorial II: Variability and Its Impact on Design.

[BibT_eX]

[DOI]

Keith A. Bowman

Sachin S. Sapatnekar

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Analytical modeling of SRAM dynamic stability.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Robust estimation of parametric yield under limited descriptions of uncertainty.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

BulletProof: a defect-tolerant CMP switch architecture.

[BibT_eX]

[DOI]

Kypros Constantinides

Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Application of fast SOCP based statistical sizing in the microprocessor design flow.

[BibT_eX]

[DOI]

Mahesh Sharma

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Towards formal probabilistic power-performance design space exploration.

[BibT_eX]

[DOI]

Joonsoo Kim

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty.

[BibT_eX]

[DOI]

Vladik Kreinovich

Proceedings of the 43rd Design Automation Conference, 2006

Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Statistical technology mapping for parametric yield.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

An efficient algorithm for statistical minimization of total power under timing yield constraints.

[BibT_eX]

[DOI]

Anirudh Devgan

Proceedings of the 42nd Design Automation Conference, 2005

2004

Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation.

[BibT_eX]

[DOI]

Michael Liu

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A New Statistical Optimization Algorithm for Gate Sizing.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Fast statistical timing analysis handling arbitrary delay correlations.

[BibT_eX]

[DOI]

Arnab Bandyopadhyay

Proceedings of the 41th Design Automation Conference, 2004

2003

Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002

Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

From blind certainty to informed uncertainty.

[BibT_eX]

[DOI]

Kurt Keutzer

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

A general probabilistic framework for worst case timing analysis.

[BibT_eX]

[DOI]

Kurt Keutzer

Proceedings of the 39th Design Automation Conference, 2002

2001

Efficient generation of pre-silicon MOS model parameters for early circuit design.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2001

2000

Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1998

A Statistical Performance Simulation Methodology for VLSI Circuits.

[BibT_eX]

[DOI]